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TMPR4925 Datasheet(PDF) 584 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 584 Page - Toshiba Semiconductor |
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584 / 590 page  Chapter 23 Pin Layout, Package 23-4 Table 23.1.2 Pin Designations (Coordinates) A1 PCICLKIO C13 ADDR[16] H1 C_BE[3] P17 Vss V13 PIO[5] A2 TMS C14 VDDC H2 PCIAD[24] P18 VDDC V14 VDDC A3 TDI C15 ADDR[11] H3 PCIAD[25] P19 DATA[5] V15 PIO[13] A4 PIO[26] C16 VDDC H4 VDDS P20 DATA[21] V16 PIO[16] A5 PIO[24] C17 Vss H17 Vss R1 PCIAD[15] V17 TEST* A6 PIO[27] C18 VDDS H18 VDDS R2 C_BE[1] V18 VDDS A7 PIO[22] C19 DQM[2] H19 DATA[12] R3 PAR V19 DATA[0] A8 PIO[19] C20 DQM[1] H20 DATA[28] R4 VDDC V20 Vss A9 SDCLKIN D1 GNT[2]* J1 PCIAD[22] R17 Vss W1 PCIAD[4] A10 SDCLK[1] D2 REQ[1]* J2 PCIAD[23] R18 DATA[19] W2 PCIAD[5] A11 SDCLK[0] D3 GNT[1]* J3 ID_SEL R19 DATA[4] W3 PCIAD[6] A12 SDCS[2]* D4 Vss J4 Vss R20 DATA[20] W4 PCIAD[7] A13 ADDR[18] D5 VDDC J17 Vss T1 PCIAD[12] W5 BWE[1]* A14 SADDR10 D6 PIO[30] J18 VDDC T2 PCIAD[13] W6 UAE A15 ADDR[13] D7 Vss J19 DATA[11] T3 PCIAD[14] W7 ADDR[0] A16 ADDR[10] D8 VDDS J20 DATA[27] T4 VDDS W8 ADDR[3] A17 ADDR[8] D9 PON* K1 PCIAD[19] T17 VDDS W9 ADDR[15] A18 ADDR[6] D10 Vss K2 PCIAD[20] T18 DATA[2] W10 CE[1]* A19 SDCS[1]* D11 VDDS K3 PCIAD[21] T19 DATA[18] W11 PIO[4] A20 RAS* D12 Vss K4 VDDS T20 DATA[3] W12 PIO[3] B1 PCICLK[1] D13 VDDS K17 Vss U1 PCIAD[9] W13 PIO[10] B2 GNT[0]* D14 Vss K18 VDDC U2 PCIAD[10] W14 PIO[9] B3 TCK D15 Vss K19 DATA[10] U3 PCIAD[11] W15 PIO[17] B4 TDO D16 VDDS K20 DATA[26] U4 Vss W16 PIO[15] B5 PIO[31] D17 Vss L1 PCIAD[17] U5 VDDS W17 NMI* B6 PIO[29] D18 WE* L2 PCIAD[18] U6 BWE[2]* W18 C32KOUT B7 PIO[21] D19 CAS* L3 VDDC U7 Vss W19 PLLVDD B8 PIO[18] D20 DQM[0] L4 Vss U8 VDDS W20 MASTERCLK B9 PIO[20] E1 PCIAD[31] L17 VDDS U9 CE[3]* Y1 PCIAD[0] B10 RESET* E2 REQ[3]* L18 DATA[24] U10 PIO[0] Y2 PCIAD[1] B11 SDCS[3]* E3 GNT[3]* L19 DATA[9] U11 Vss Y3 PCIAD[2] B12 CKE E4 REQ[2]* L20 DATA[25] U12 VDDS Y4 PCIAD[3] B13 ADDR[19] E17 Vss M1 FRAME* U13 PIO[6] Y5 SYSCLK B14 ADDR[14] E18 VDDS M2 C_BE[2] U14 Vss Y6 SWE* B15 ADDR[12] E19 DATA[31] M3 PCIAD[16] U15 PIO[7] Y7 ADDR[1] B16 ADDR[9] E20 RP* M4 VDDS U16 Vss Y8 ADDR[4] B17 ADDR[7] F1 PCIAD[28] M17 Vss U17 Vss Y9 OE* B18 ADDR[5] F2 PCIAD[29] M18 DATA[7] U18 DATA[16] Y10 CE[0]* B19 DQM[3] F3 PCIAD[30] M19 DATA[23] U19 DATA[1] Y11 BUSSPRT B20 SDCS[0]* F4 VDDS M20 DATA[8] U20 DATA[17] Y12 ACK* C1 PCICLK[2] F17 Vss N1 STOP* V1 C_BE[0] Y13 PIO[11] C2 REQ[0]* F18 DATA[14] N2 DEVSEL* V2 PCIAD[8] Y14 PIO[8] C3 VDDS F19 DATA[30] N3 TRDY* V3 VDDS Y15 PIO[12] C4 VDDC F20 DATA[15] N4 IRDY* V4 VDDC Y16 PIO[14] C5 PIO[25] G1 PCIAD[26] N17 Vss V5 BWE[0]* Y17 BC32K C6 PIO[28] G2 PCIAD[27] N18 VDDS V6 BWE[3]* Y18 C32KIN C7 VDDC G3 VDDC N19 DATA[6] V7 VDDC Y19 PLLVSS C8 PIO[23] G4 Vss N20 DATA[22] V8 ADDR[2] Y20 Vss C9 TRST* G17 Vss P1 SERR* V9 CE[2]* C10 VDDC G18 VDDC P2 PERR* V10 PIO[2] C11 SCANENB* G19 DATA[13] P3 VDDC V11 VDDC C12 ADDR [17] G20 DATA[29] P4 Vss V12 PIO[1] |
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