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TMPR4925 Datasheet(PDF) 585 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 585 Page - Toshiba Semiconductor |
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585 / 590 page  Chapter 23 Pin Layout, Package 23-5 Table 23.1.3 Pin Designations (Signal name) Y12 ACK* G19 DATA[13] L1 PCIAD[17] Y19 PLLVSS D13 VDDS W7 ADDR[0] F18 DATA[14] L2 PCIAD[18] D9 PON* D16 VDDS Y7 ADDR[1] F20 DATA[15] K1 PCIAD[19] A20 RAS* E18 VDDS V8 ADDR[2] U18 DATA[16] K2 PCIAD[20] C2 REQ[0]* F4 VDDS W8 ADDR[3] U20 DATA[17] K3 PCIAD[21] D2 REQ[1]* H4 VDDS Y8 ADDR[4] T19 DATA[18] J1 PCIAD[22] E4 REQ[2]* H18 VDDS B18 ADDR[5] R18 DATA[19] J2 PCIAD[23] E2 REQ[3]* K4 VDDS A18 ADDR[6] R20 DATA[20] H2 PCIAD[24] B10 RESET* L17 VDDS B17 ADDR[7] P20 DATA[21] H3 PCIAD[25] E20 RP* M4 VDDS A17 ADDR[8] N20 DATA[22] G1 PCIAD[26] A14 SADDR10 N18 VDDS B16 ADDR[9] M19 DATA[23] G2 PCIAD[27] C11 SCANENB* T4 VDDS A16 ADDR[10] L18 DATA[24] F1 PCIAD[28] A11 SDCLK[0] T17 VDDS C15 ADDR[11] L20 DATA[25] F2 PCIAD[29] A10 SDCLK[1] U5 VDDS B15 ADDR[12] K20 DATA[26] F3 PCIAD[30] A9 SDCLKIN U8 VDDS A15 ADDR[13] J20 DATA[27] E1 PCIAD[31] B20 SDCS[0]* U12 VDDS B14 ADDR[14] H20 DATA[28] B1 PCICLK[1] A19 SDCS[1]* V3 VDDS W9 ADDR[15] G20 DATA[29] C1 PCICLK[2] A12 SDCS[2]* V18 VDDS C13 ADDR[16] F19 DATA[30] A1 PCICLKIO B11 SDCS[3]* C17 Vss C12 ADDR[17] E19 DATA[31] P2 PERR* P1 SERR* D4 Vss A13 ADDR[18] N2 DEVSEL* U10 PIO[0] N1 STOP* D7 Vss B13 ADDR[19] D20 DQM[0] V12 PIO[1] Y6 SWE* D10 Vss Y17 BC32K C20 DQM[1] V10 PIO[2] Y5 SYSCLK D12 Vss Y11 BUSSPRT C19 DQM[2] W12 PIO[3] B3 TCK D14 Vss V5 BWE[0]* B19 DQM[3] W11 PIO[4] A3 TDI D15 Vss W5 BWE[1]* M1 FRAME* V13 PIO[5] B4 TDO D17 Vss U6 BWE[2]* B2 GNT[0]* U13 PIO[6] V17 TEST* E17 Vss V6 BWE[3]* D3 GNT[1]* U15 PIO[7] A2 TMS F17 Vss D19 CAS* D1 GNT[2]* Y14 PIO[8] N3 TRDY* G4 Vss Y10 CE[0]* E3 GNT[3]* W14 PIO[9] C9 TRST* G17 Vss W10 CE[1]* J3 ID_SEL W13 PIO[10] W6 UAE H17 Vss V9 CE[2]* N4 IRDY* Y13 PIO[11] C4 VDDC J4 Vss U9 CE[3]* W20 MASTERCLK Y15 PIO[12] C7 VDDC J17 Vss B12 CKE W17 NMI* V15 PIO[13] C10 VDDC K17 Vss Y18 C32KIN Y9 OE* Y16 PIO[14] C14 VDDC L4 Vss W18 C32KOUT R3 PAR W16 PIO[15] C16 VDDC M17 Vss V1 C_BE[0] Y1 PCIAD[0] V16 PIO[16] D5 VDDC N17 Vss R2 C_BE[1] Y2 PCIAD[1] W15 PIO[17] G3 VDDC P4 Vss M2 C_BE[2] Y3 PCIAD[2] B8 PIO[18] G18 VDDC P17 Vss H1 C_BE[3] Y4 PCIAD[3] A8 PIO[19] J18 VDDC R17 Vss V19 DATA[0] W1 PCIAD[4] B9 PIO[20] K18 VDDC U4 Vss U19 DATA[1] W2 PCIAD[5] B7 PIO[21] L3 VDDC U7 Vss T18 DATA[2] W3 PCIAD[6] A7 PIO[22] P3 VDDC U11 Vss T20 DATA[3] W4 PCIAD[7] C8 PIO[23] P18 VDDC U14 Vss R19 DATA[4] V2 PCIAD[8] A5 PIO[24] R4 VDDC U16 Vss P19 DATA[5] U1 PCIAD[9] C5 PIO[25] V4 VDDC U17 Vss N19 DATA[6] U2 PCIAD[10] A4 PIO[26] V7 VDDC V20 Vss M18 DATA[7] U3 PCIAD[11] A6 PIO[27] V11 VDDC Y20 Vss M20 DATA[8] T1 PCIAD[12] C6 PIO[28] V14 VDDC D18 Vss L19 DATA[9] T2 PCIAD[13] B6 PIO[29] C3 VDDS K19 DATA[10] T3 PCIAD[14] D6 PIO[30] C18 VDDS J19 DATA[11] R1 PCIAD[15] B5 PIO[31] D8 VDDS H19 DATA[12] M3 PCIAD[16] W19 PLLVDD D11 VDDS |
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