TMPR4925 datasheet(589/590 Pages) TOSHIBA

589 / 590 page

Appendix A TX49/H2 Core Supplement

A-1

Appendix A.

TX49/H2 Core Supplement

This section explains items that are unique to the TX4925 of the TX49/H2 Core. Please refer to the “64-bit

TX System RISC TX49/H2 Core Architecture” for more information regarding the TX49/H2 Core.

A.1

Processor ID

PRId Register values of the TX4925 TX49/H2 Core are as follows.

Processor Revision Identifier Register: 0x0000_2D23

FPU Implementation/Revision Register (FCR0): 0x0000_2D21

These values may be changed at a later date. Please contact the Toshiba Engineering Department for the

most recent information.

A.2

Interrupts

Interrupt signalling of the on-chip interrupt controller is reflected in bit IP[2] of the Cause Register in the

TX49/H2 Core. In addition, interrupt causes are reflected in other bits of the IP field. Please refer to Section

“15.3.5 Interrupt Notification” for more information.

A.3

Bus Snoop

The Bus Snoop function is not used with the TX4925 due to restrictions of the Bus Snoop specification.

A.4

Halt/Doze Mode

The Doze mode is not necessary when the Bus Snoop function is not used. Please use the Halt mode,

which further reduces power consumption. Clearing the HALT bit of the Config Register makes it possible to

shift to the Halt mode by executing the WAIT instruction.

A.5

Memory Access Order

The TX49/H2 Core has a 4-stage Write buffer, the PCI Bus Bridge (PCI Controller) has 4 stages for

initiator access, and has a 2-stage Post Write buffer (Write buffer) for target access.

When data enters the Write buffer of the TX49/H2 Core, Cache Refill Read operations that do not match

the address of that data after the Write is issued may be issued to the internal bus (G-Bus) before the Write.

Other accesses are issued in order.

Executing the SYNC instruction guarantees that bus access invoked by a load/store instruction previously

executed will be complete on the internal bus.

The PCI Bus Bridge is issued by the issue destination bus in the order all bus accesses are issued on the

issue source bus. Please refer to “10.3.6 Post Write Function” for more information regarding methods for

guaranteeing the completion of Write transactions of the Post Write Buffer.

TMPR4925 Datasheet(PDF) 589 Page - Toshiba Semiconductor