MA780 – 8-BIT TO 12-BIT LOW-POWER ANGLE SENSOR

MA780 Rev. 1.2

MonolithicPower.com

11

8/30/2021

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/CS

MISO

MOSI

MSB

SCLK

Hi-Z

LSB

X

MSB

tMISO

tCSL

tMOSI

tSCLKL tSCLKH

tSCLK

tMISO

tMOSI

tIDLE_ANGLE

tMISO

MSB

Hi-Z

X

MSB

LSB

tCSH

tSTORE_ALL_REG_TO_NVM

tRESTORE_ALL_REG_FROM_NVM

tSTORE_REG_TO_NVM

tCLEAR_FAULT

tIDLE_WRITE_REG

tIDLE_READ_REG

Figure 12: SPI Timing Diagram (Mode 3)

/CS

MISO

MOSI

Angle

0

Angle

Angle

Angle

0

0

Read Reg.

Command

Reg Value

0

Angle

0

Angle

Write Reg.

Command

Reg Value

0

Angle

0

tIDLE_ANGLE

tIDLE_ANGLE

tIDLE_ANGLE

tIDLE_READ_REG

tIDLE_ANGLE

tIDLE_READ_REG

tIDLE_WRITE_REG

tIDLE_WRITE_REG

Figure 13: Minimum Idle Time

Table 4: SPI Timing

Parameter (7)

Description

Min

Max

Unit

tIDLE_ANGLE

Idle time between two subsequent angle transmissions

120

ns

tIDLE_READ_REG

Idle time before and after a register readout

120

ns

tIDLE_WRITE_REG

Idle time before and after a register write.

120

ns

tSTORE_REG_TO_NVM

Time required to store a register value to the NVM

23

ms

tSTORE_ALL_REGT_O_NVM

Time required to store all register values to the NVM

704

ms

tRESTORE_ALL_REG_FROM_NVM

Time required to restore all register values from the NVM

240

µs

tCLEAR_FAULT

Time required to clear the fault flags (register 26)

40

ns

tCSL

Time between /CS falling edge and SCLK falling edge

120

ns

tSCLK

SCLK period

40

ns

tSCLKL

Low level of the SCLK signal

20

ns

tSCLKH

High level of the SCLK signal

20

ns

tCSH

Time between the SCLK rising edge and /CS rising edge

20

ns

tMISO

SCLK falling edge to data output valid

15

ns

tMOSI

Data input valid to SCLK reading edge

15

ns

Note:

7) All values are guaranteed by design.