ADT7516 datasheet(5/44 Pages) AD

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ADT7516/ADT7517/ADT7519

Rev. B | Page 5 of 44

Parameter1

Min

Typ

Max

Unit

Conditions/Comments

ON-CHIP REFERENCE

Reference Voltage4

2.2662

2.28

2.2938

Temperature Coefficient4

ppm/°C

OUTPUT CHARACTERISTICS4

Output Voltage6

0.001

VDD − 0.1

This is a measure of the minimum and maximum

drive capability of the output amplifier

DC Output Impedance

0.5

Short Circuit Current

VDD = 5 V

VDD = 3 V

Power-Up Time

2.5

μs

Coming out of power-down mode, VDD = 5 V

μs

Coming out of power-down mode, VDD = 3.3 V

DIGITAL INPUTS4

Input Current

±1

μA

VIN = 0 V to VDD

VIL, Input Low Voltage

0.8

VIH, Input High Voltage

1.89

Pin Capacitance

All digital inputs

SCL, SDA Glitch Rejection

Input filtering suppresses noise spikes of less

than 50 ns

LDAC Pulse Width

Edge triggered input

DIGITAL OUTPUT

Digital High Voltage, VOH

2.4

ISOURCE = ISINK = 200 μA

Output Low Voltage, VOL

0.4

IOL = 3 mA

Output High Current, IOH

VOH = 5 V

Output Capacitance, COUT

INT/INT Output Saturation Voltage

0.8

IOUT = 4 mA

I2C TIMING CHARACTERISTICS7, 8

Serial Clock Period, t1

2.5

μs

Fast mode I2C, see Figure 2

Data In Setup Time to SCL High, t2

Data Out Stable after SCL Low, t3

See Figure 2

SDA Low Setup Time to SCL

Low (Start Condition), t4

See Figure 2

SDA High Hold Time after SCL

High (Stop Condition), t5

See Figure 2

SDA and SCL Fall Time, t6

300

See Figure 2

SDA and SCL Rise Time, t7

3009

See Figure 2

SPI TIMING CHARACTERISTICS4, 10

CS to SCLK Setup Time, t1

See Figure 3

SCLK High Pulse Width, t2

See Figure 3

SCLK Low Pulse Width, t3

See Figure 3

Data Access Time after SCLK

Falling Edge, t411

Data Setup Time Prior to SCLK

Rising Edge, t5

See Figure 3

Data Hold Time after SCLK

Rising Edge, t6

See Figure 3

CS to SCLK Hold Time, t7

μs

See Figure 3

CS to DOUT High Impedance, t8

See Figure 3

POWER REQUIREMENTS

VDD

2.7

5.5

VDD Settling Time

VDD settles to within 10% of its final voltage level

IDD (Normal Mode)12

VDD = 3.3 V, VIH = VDD, and VIL = GND

2.2

VDD = 5 V, VIH = VDD, and VIL = GND

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