ADT7516 datasheet(24/44 Pages) AD

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ADT7516/ADT7517/ADT7519

Rev. B | Page 24 of 44

4pF

AIN

100Ω

Figure 52. Equivalent Analog Input ESD Circuit

AIN Interrupts

The measured results from the AIN inputs are compared with

the AIN VHIGH (greater than comparison) and VLOW (less than or

equal to comparison) limits. An interrupt occurs if the AIN

inputs exceed or equal the limit registers. These voltage limits

are stored in on-chip registers. Note that the limit registers are

8 bits long and the AIN conversion result is 10 bits long. If the

voltage limits are not masked out, then any out-of-limit compari-

sons generate flags that are stored in the Interrupt Status 1

cause the INT/INT output to pull either high or low depending

on the output polarity setting. It is good design practice to mask

out interrupts for channels that are of no concern to the

application. Figure 53 shows the interrupt structure for the

ADT7516/ ADT7517/ADT7519. It gives a block diagram

representation of how the various measurement channels affect

the INT/INT pin.

WATCHDOG

LIMIT

COMPARISONS

INTERRUPT

MASK

REGISTERS

CONTROL

CONFIGURATION

INTERRUPT

STATUS

(TEMP AND

AIN1 TO AIN4)

INTERRUPT

STATUS

(VDD)

READ RESET

S/W RESET

INTERNAL

TEMP

INT/INT

(LATCHED OUTPUT)

INT/INT

ENABLE BIT

EXTERNAL

TEMP

VDD

DIODE

FAULT

AIN1 TO AIN4

Figure 53. ADT7516/ADT7517/ADT7519 Interrupt Structure

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