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ADT7516 Datasheet(PDF) 29 Page - Analog Devices |
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ADT7516 Datasheet(HTML) 29 Page - Analog Devices |
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29 / 44 page ![]() ADT7516/ADT7517/ADT7519 Rev. B | Page 29 of 44 R/W Address Name Power-On Default 0x14 DAC C LSBs (ADT7516/ADT7517 only) 0x00 0x15 DAC C MSBs 0x00 0x16 DAC D LSBs (ADT7516/ADT7517 only) 0x00 0x17 DAC D MSBs 0x00 0x18 Control Configuration 1 0x00 0x19 Control Configuration 2 0x00 0x1A Control Configuration 3 0x00 0x1B DAC Configuration 0x00 0x1C LDAC Configuration 0x00 0x1D Interrupt Mask 1 0x00 0x1E Interrupt Mask 2 0x00 0x1F Internal Temp Offset 0x00 0x20 External Temp Offset 0x00 0x21 Internal Analog Temp Offset 0xD8 0x22 External Analog Temp Offset 0xD8 0x23 VDD VHIGH Limit 0xC7 0x24 VDD VLOW Limit 0x62 0x25 Internal THIGH Limit 0x64 0x26 Internal TLOW Limit 0xC9 0x27 External THIGH/AIN1 VHIGH Limits 0xFF 0x28 External TLOW/AIN1 VLOW Limits 0x00 0x29 to 0x2A Reserved 0x2B AIN2 VHIGH Limit 0xFF 0x2C AIN2 VLOW Limit 0x 00 0x2D AIN3 VHIGH Limit 0xFF 0x2E AIN3 VLOW Limit 0x00 0x2F AIN4 VHIGH Limit 0xFF 0x30 AIN4 VLOW Limit 0x00 0x31 to 0x4C Reserved 0x4D Device ID 0x03/0x0B/0x07 0x4E Manufacturer’s ID 0x41 0x4F Silicon Revision Check register for current silicon revision 0x50 to 0x7E Reserved 0x00 0x7F SPI Lock Status 0x00 0x80 to 0xFF Reserved 0x00 Interrupt Status 1 Register (Read-Only) [Address 0x00] This 8-bit read-only register reflects the status of some of the interrupts that can cause the INT/INT pin to go active. This register is reset by a read operation, provided that any out-of- limit event has been corrected. It is also reset by a software reset. D7 D6 D5 D4 D3 D2 D1 D0 01 01 01 01 01 01 01 01 1 Default settings at power-up. Table 11. Bit Function D0 1 when the internal temperature value exceeds THIGH limit. Any internal temperature reading greater than the set limit causes an out-of-limit event. D1 1 when internal temperature value exceeds TLOW limit. Any internal temperature reading less than or equal to the set limit causes an out-of-limit event. D2 This status bit is linked to the configuration of Pin 7 and Pin 8. If configured for external temperature sensor, this bit is 1 when the external temperature value exceeds THIGH limit. The default value for this limit register is –1°C, so any external temperature reading greater than the set limit causes an out-of-limit event. If configured for AIN1 and AIN2, this bit is 1 when AIN1 input voltage exceeds VHIGH or VLOW limits. D3 1 when external temperature value exceeds TLOW limit. The default value for this limit register is 0°C, so any external temperature reading less than or equal to the set limit causes an out-of-limit event. D4 1 indicates a fault (open or short) for the external temperature sensor. D5 1 when AIN2 voltage is greater than its corresponding VHIGH limit. 1 when AIN2 voltage is less than or equal to its corresponding VLOW limit. D6 1 when AIN3 voltage is greater than its corresponding VHIGH limit. 1 when AIN3 voltage is less than or equal to its corresponding VLOW limit. D7 1 when AIN4 voltage is greater than its corresponding VHIGH limit. 1 when AIN4 voltage is less than or equal to its corresponding VLOW limit. Interrupt Status 2 Register (Read-Only) [Address = 0x01] This 8-bit read-only register reflects the status of the VDD interrupt that can cause the INT/INT pin to go active. This register is reset by a read operation, provided that any out-of- limit event has been corrected. It is also reset by a software reset. D7 D6 D5 D4 D3 D2 D1 D0 N/A N/A N/A 01 N/A N/A N/A N/A 1 Default settings at power-up. Table 12. Bit Function D4 1 when VDD value is greater than its corresponding VHIGH limit. 1 when VDD is less than or equal to its corresponding VLOW limit. Internal Temperature Value/VDD Value Register LSBs (Read-Only) [Address = 0x03] This 8-bit read-only register stores the two LSBs of the 10-bit temperature reading from the internal temperature sensor and the two LSBs of the 10-bit supply voltage reading. D7 D6 D5 D4 D3 D2 D1 D0 N/A N/A N/A N/A V1 LSB T1 LSB N/A N/A N/A N/A 01 01 01 01 1 Default settings at power-up. |
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