ATMEGA640 datasheet(173/449 Pages) ATMEL

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173

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-

ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,

resonator, and capacitors) tolerances, it is recommended that maximum frequency of an

external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 62. Prescaler for synchronous Timer/Counters

GTCCR – General

Timer/Counter Control

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this

mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keep-

ing the corresponding prescaler reset signals asserted. This ensures that the

corresponding Timer/Counters are halted and can be configured to the same value with-

out the risk of one of them advancing during configuration. When the TSM bit is written

to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the

Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters

When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4

and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by

hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1,

Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler and a

reset of this prescaler will affect all timers.

PSR10

Clear

clk

I/O

Synchronization

TIMER/COUNTERn CLOCK SOURCE

clk

TIMER/COUNTERn CLOCK SOURCE

clk

CSn0

CSn1

CSn2

CSn0

CSn1

CSn2

Bit

0x23 (0x43)

TSM

–

PSRASY PSRSYNC

GTCCR

Read/Write

R/W

Initial Value

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