RF112 datasheet(29/45 Pages) NXP

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Table 6. isolation between RF pins (continued)

TX_HB_

OUT

3.6 Frequency generation specification

Several LO-signals and clocks have to be generated independently in RF112 Transceiver.

To retain the RF path coherence after power-up, all the synthesizers as well as all LO

dividers must be running all the time after power on. The frequency dividers must be able

to track the frequency while tuning, not missing any clock pulses, so that the mixer

phases will be the same when returning to the same frequency after a frequency change.

The TRX and the two observation receiver chains each require its own synthesizers. The

clocks used by the LVDS interfaces are generated internally in the LVDS IP and are

consequently not described here. An overview of the LO and clock generation

architecture is shown in the figure below.

CORE

CMOS

input

LVDS_160M_IO_P

LVDS_160M_IO_N

fref_trx

fref_obs1

fref_obs2

dig_clk_40M

PFD

Integer part

Fractional part

dig_clk_160M

ext_clk_160M

VCO

TRX Synthesizer

TX HB path

TX_HB_LO_I

TX_HB_LO_Q

Charge

pump

∑

Mod.

Loop

filter

19.2 - 24.0 GHz

PFD

Integer part

Fractional part

VCO

RO2 Synthesizer

Charge

pump

∑

Mod.

Loop

filter

19.2 - 24.0 GHz

PFD

Integer part

Fractional part

VCO

RO1 Synthesizer

Charge

pump

∑

Mod.

Loop

filter

19.2 - 24.0 GHz

REF

RX2 HB path

RX2_HB_LO_I

RX2_HB_LO_Q

TX LB path

TX_LB_LO_I

TX_LB_LO_Q

RX2 LB path

RX2_LB_LO_I

RX2_LB_LO_Q

RX1 HB path

RX1_HB_LO_I

RX1_HB_LO_Q

RX1 LB path

RX1_LB_LO_I

RX1_LB_LO_Q

RO2 HB path

RO2_HB_LO_I

RO2_HB_LO_Q

RO2 WPLL

RO1 WPLL

WBPLL

RO1 HB path

RO1_HB_LO_I

RO1_HB_LO_Q

RO1 HB path

RO1_LB_LO_I

RO1_LB_LO_Q

Figure 16. LO and clock generation block diagram

The transmitters require very low wideband noise. The LOs for the TRX are therefore

generated from a high frequency VCO running at four or eight times the LO frequency.

Electrical characteristics

RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024

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