RF112 datasheet(14/45 Pages) NXP

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Table 3. Recommended operating conditions (continued)

Characteristic

Symbol

Min

Typ

Max

Unit

Notes

Input external

clock differential

input voltage

level

LVDS_160M_IO_P/N

Input

200

400

mVpp

Input external

clock input

common mode

voltage level

LVDS_160M_IO_P/N

Input

0.2

1.2

Input external

clock duty cycle

LVDS_160M_IO_P/N

Input

Output

reference clock

output load

LVDS_160M_IO_P/N

output

100

Rx BB external

output load (kick

-back filter)

TX BB input

common mode

0.5

TX BB input

signal level

Full scale from DAC

0.35

Frequency

Range

HB Lowest

4900

MHz

HB Highest

6000

MHz

LB Lowest

2400

MHz

LB Highest

2500

MHz

3.1.3 Power Sequencing

Power rails can ramp simultaneously for all voltages, Core power

suppliesVDD_DIG_CORE (0.9V ) should not begin to ramp before other supplies, and

should reach 90% of nominal voltage no more than 5ms after I/O rails ramp as shown in

the figure below. Analog 1.67 V supply and I/O 1.8 V supply are expected to begin ramp

simultaneously.

Electrical characteristics

RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024

NXP Semiconductors

RF112 Datasheet(PDF) 14 Page - NXP Semiconductors

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