RF112 datasheet(37/45 Pages) NXP

37 / 45 page

GND

Vos

150 mVpp

0V differential

Vocm

Vod

Figure 24. Output Offset Voltage Imbalance Waveform

3.8 Device start-up

The RF112 Transceiver is not equipped with any on-chip power-on-reset functionality.

Instead the transceiver has a dedicated reset pin, RESETN, which has the functionality

resetn

in operational mode. The RF112 Transceiver is asynchronously reset whenever the

resetn

signal is low. To properly leave the reset mode a stable glitch free clock is

required. Therefore, the reset values of the XO and the regulator powering it are such that

the XO automatically starts up regardless of whether a crystal is mounted or an external

clock is provided. The reset condition must not be released, that is resetn set high, until

all supply voltages have been stable long enough to allow the XO to start up and provide

a glitch free clock. If an external clock is provided to the RF112 Transceiver, then reset

must not be released until the quality of that clock can be guaranteed.

Table 10. Start-up specification

Parameter

Conditions

Min

Typ

Max

Unit

Minimum reset time Crystal oscillator

Maximum DLL

calibration time

700

μs

Upon power-up and release from reset, the chip has its 160 MHz differential clock IO

buffer tri-stated. It has the internal crystal oscillator enabled to generate a 40 MHz clock,

and that clock is driven to internal components to allow configuration via the I2C and/or

the LLCP interfaces.

The firmware download and further configuration are possible over either the I2C or

LLCP (running at 100 Mbps) interfaces.

After firmware download and a command to calibrate the DLL, the completion of

calibration is reported in a register that can be polled over the LLCP or I2C interfaces.

Electrical characteristics

RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024

NXP Semiconductors

RF112 Datasheet(PDF) 37 Page - NXP Semiconductors

RF112 Datasheet(HTML) 37 Page - NXP Semiconductors

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