RF112 datasheet(6/45 Pages) NXP

6 / 45 page

The analog filter bandwidths of the two TRX receivers are always the same. However,

the bandwidth selection of the receivers and transmitters are completely independent. The

bandwidth setting of the observation receivers are independent of both the TRX receivers

and transmitters and of the other observation receiver.

Below is the RF112 block diagram of the Transceiver digital controller:

COMMAND

OTP

INCL. CTRL.

WDOG

ASP

PROGRAM

RAM

PMEM

ACCESS

PAD

CONTROL

DBG

ASP TOP

XBUS

CORDIC

lin2log/log2lin

BIST

halt

dbg

data

RAM-1

ENABLE

COUNTER A

ENABLE

COUNTER B

MAP

RSBUS

MASTER

FREQ

COUNT

AUX ADC

CGU

ANALOG

40/160 MHz

RSBUS SLAVES

∑ MODULATOR

(TRX SYNTH)

∑ MODULATOR

(OBS1 SYNTH)

∑ MODULATOR

(OBS2 SYNTH)

RX/TX gain

RSSI data 4x2 bits

GAIN

RSSI

DECODER

S1 S2

APB

I2C

APB

GO-PULSE

GENERATOR

TIMER A

TIMER B

JTAG

LVDS

PINMUX

APB

LLCP

INT

APB

BIST

data

RAM-2

Figure 3. RF112 Digital Block Diagram

The digital part of RF112 consists of an ASP and a number of digital hardware blocks,

and interfaces both with the analogue part - via an RS bus, signals, and clocks - and with

the outside world - via LLCP and I2C interfaces. The internal clock frequency is 160

MHz in normal operation, during boot a 40 MHz clock is used. The digital part is used to

control and calibrate the analog part of the chip, both RF and baseband signal interfaces

are analog.

Introduction

RF112 Transceiver Data Sheet, Rev. 1 Draft B, 05/2024

NXP Semiconductors

RF112 Datasheet(PDF) 6 Page - NXP Semiconductors

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