XRT86VL34 datasheet(20/156 Pages) EXAR

20 / 156 page

XRT86VL34

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. V1.2.0

FASTSYNC

R/W

Faster Sync Algorithm

This bit is used to specify one of the synchronization criteria that the

Receive T1 Framer block employs. If this “Faster Sync Algorithm” is

enabled, the Receive T1 Framer Block will declare synchronization

earlier. The table below specifies the number of consecutive frames

with correct F-bits that the T1 Receive framer must receive in order

to declare “SYNC” when FASTSYNC is enabled or disabled.

0 - Disables FASTSYNC feature.

1 - Enables FASTSYNC feature.

2-0

FSl[2:0]

R/W

000

T1 Framing Mode Select [2:0]

These three bits permit the user to select the exact T1 framing format

that the channel is to operate in.

Bit 2 is MSB and Bit 0 is LSB. The following table shows the five dif-

ferent framing formats that can be selected by configuring these

three bits accordingly.

NOTE: Changing Framing formats 'on the fly' will cause the Receive

T1 Framer block to undergo a “Reframe” event.

TABLE 4: FRAMING SELECT REGISTER (FSR)

HEX ADDRESS: 0Xn107

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

Framing

FastSync

= 0

FastSync

= 1

ESF

SLC

® 96

Framing

FS[2]

FS[1]

FS[0]

ESF

T1DM

SLC

®96

XRT86VL34 Datasheet(PDF) 20 Page - Exar Corporation

XRT86VL34 Datasheet(HTML) 20 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL