XRT86VL34 datasheet(36/156 Pages) EXAR

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XRT86VL34

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. V1.2.0

Tx_FCS_EN

R/W

Transmit LAPD Message with Frame Check Sequence (FCS)

This bit permits the user to configure the Transmit HDLC Controller

block # 1 to compute and append FCS octets to the “back-end” of

each outbound MOS data-link message.

0 - Configures the Transmit HDLC Controller block # 1 to NOT com-

pute and append the FCS octets to the back-end of each outbound

MOS data-link message.

1 - Configures the Transmit HDLC Controller block # 1 TO COM-

PUTE and append the FCS octets to the back-end of each outbound

MOS data-link message.

NOTE: This bit is ignored if the transmit HDLC1 controller has been

configured to operate in the BOS mode - bit 0 (MOS/BOS)

within this register is set to 0.

MOS/BOS

R/W

Message Oriented Signaling/Bit Oriented Signaling Send

This bit permits the user to enable LAPD transmission through

HDLC Controller Block # 1 using either BOS (Bit-Oriented Signaling)

or MOS (Message-Oriented Signaling) frames.

0 - Transmit HDLC Controller block # 1 BOS message Send.

1 - Transmit HDLC Controller block # 1 MOS message Send.

NOTE: This is not an Enable bit. This bit must be set to "0" each time

a BOS is to be sent.

TABLE 16: DATA LINK CONTROL REGISTER (DLCR1)

HEX ADDRESS: 0Xn113

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

XRT86VL34 Datasheet(PDF) 36 Page - Exar Corporation