XRT86VL34 datasheet(93/156 Pages) EXAR

93 / 156 page

XRT86VL34

REV. V1.2.0

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 78: BLOCK INTERRUPT STATUS REGISTER (BISR)

HEX ADDRESS: 0XnB00

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

Reserved

For E1 mode only

LBCODE

Loopback Code Block Interrupt Status

This bit indicates whether or not the Loopback Code block has an

interrupt request awaiting service.

0 - Indicates no outstanding Loopback Code Block interrupt request

is awaiting service

1 - Indicates the Loopback Code block has an interrupt request

awaiting service. Interrupt Service routine should branch to the inter-

rupt source and read the Loopback Code Interrupt Status register

(address 0xnB0A) to clear the interrupt

NOTE:

This bit will be reset to 0 after the microprocessor has

performed a read to the Loopback Code Interrupt Status

RxClkLOS

Loss of Recovered Clock Interrupt Status

This bit indicates whether or not the T1 receive framer is currently

declaring the "Loss of Recovered Clock" interrupt.

0 = Indicates that the T1 Receive Framer Block is NOT currently

declaring the "Loss of Recovered Clock" interrupt.

1 = Indicates that the T1 Receive Framer Block is currently declar-

ing the "Loss of Recovered Clock" interrupt.

NOTE: This bit is only active if the clock loss detection feature is

enabled (Register - 0xn100)

ONESEC

One Second Interrupt Status

This bit indicates whether or not the T1 receive framer block is cur-

rently declaring the "One Second" interrupt.

0 = Indicates that the T1 Receive Framer Block is NOT currently

declaring the "One Second" interrupt.

1 = Indicates that the T1 Receive Framer Block is currently declar-

ing the "One Second" interrupt.

HDLC

HDLC Block Interrupt Status

This bit indicates whether or not the HDLC block has any interrupt

request awaiting service.

0 = Indicates no outstanding HDLC block interrupt request is await-

ing service

1 = Indicates HDLC Block has an interrupt request awaiting service.

Interrupt Service routine should branch to the interrupt source and

read the corresponding Data LInk Status Registers (address

0xnB06, 0xnB16, 0xnB26, 0xnB10, 0xnB18, 0xnB28) to clear the

interrupt.

NOTE:

This bit will be reset to 0 after the microprocessor has

performed a read to the corresponding Data Link Status

Registers that generated the interrupt.

XRT86VL34 Datasheet(PDF) 93 Page - Exar Corporation

XRT86VL34 Datasheet(HTML) 93 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL