XRT86VL34 datasheet(25/156 Pages) EXAR

25 / 156 page

XRT86VL34

REV. V1.2.0

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 8: SYNCHRONIZATION MUX REGISTER (SMR)

HEX ADDRESS: 0Xn109

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

Reserved

MFRAMEALIGN

R/W

Transmit Multiframe Sync Alignment

This bit forces Transmit T1 framer block to align with the backplane

multiframe boundary (TxMSYNC_n).

0 = Do not force the transmit T1 framer block to align with the TxM-

SYNC signal.

1 = Force the transmit T1 framer block to align with the TxMSYNC

signal.

NOTE: This bit is not used in base rate (1.544MHz Clock) mode.

MSYNC

R/W

Transmit Super Frame Boundary

This bit provides an option to use the transmit single frame boundary

(TxSYNC) as the transmit multi-frame boundary (TxMSYNC) in high

speed or multiplexed modes. In 1.544MHz clock mode (base rate),

the TxMSYNC is used as the transmit superframe boundary, in other

clock modes (i.e. high speed or multiplexed modes), TxMSYNC is

used as an input transmit clock for the backplane interface.

0 = Configures the TxSYNC as a single frame boundary.

1 = Configures the TxSYNC as a superframe boundary (TxMSYNC)

in high-speed or multiplexed mode.

NOTE: This bit is not used in base rate (1.544MHz Clock) mode.

XRT86VL34 Datasheet(PDF) 25 Page - Exar Corporation