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XRT86VL34 Datasheet(PDF) 88 Page - Exar Corporation |
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XRT86VL34 Datasheet(HTML) 88 Page - Exar Corporation |
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88 / 156 page  XRT86VL34 83 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0 TABLE 65: PMON RECEIVE CRC-6 BIT ERROR COUNTER - MSB (RSBBECU) HEX ADDRESS: 0Xn905 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 RSBBEC[15] RUR 0 Performance Monitor “Receive Synchronization Bit Error 16-Bit Counter” - Upper Byte: These RESET-upon-READ bits, along with that within the “PMON Receive Synchronization Bit Error Counter Register LSB” combine to reflect the cumulative number of instances that the Receive Syn- chronization Bit errors has been detected by the Receive T1 Framer block since the last read of this register. This register contains the Most Significant byte of this 16-bit of the Receive Synchronization Bit Error counter. NOTE: For all 16-bit wide PMON registers, user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts. To clear PMON count, user must read the MSB counter first before reading the LSB counter in order to clear the PMON count. 6 RSBBEC[14] RUR 0 5 RSBBEC[13] RUR 0 4 RSBBEC[12] RUR 0 3 RSBBEC[11] RUR 0 2 RSBBEC[10] RUR 0 1 RSBBEC[9] RUR 0 0 RSBBEC[8] RUR 0 TABLE 66: PMON RECEIVE CRC-6 BIT ERROR COUNTER - LSB (RSBBECL) HEX ADDRESS: 0Xn906 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 RSBBEC[7] RUR 0 Performance Monitor “Receive Synchronization Bit Error 16-Bit Counter” - Lower Byte: These RESET-upon-READ bits, along with that within the “PMON Receive Synchronization Bit Error Counter Register MSB” combine to reflect the cumulative number of instances that the Receive Syn- chronization Bit errors has been detected by the Receive T1 Framer block since the last read of this register. This register contains the Least Significant byte of this 16-bit of the Receive Synchronization Bit Error counter. NOTE: For all 16-bit wide PMON registers, user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts. To clear PMON count, user must read the MSB counter first before reading the LSB counter in order to clear the PMON count. 6 RSBBEC[6] RUR 0 5 RSBBEC[5] RUR 0 4 RSBBEC[4] RUR 0 3 RSBBEC[3] RUR 0 2 RSBBEC[2] RUR 0 1 RSBBEC[1] RUR 0 0 RSBBEC[0] RUR 0 |
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