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XRT86VL34 Datasheet(PDF) 85 Page - Exar Corporation |
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XRT86VL34 Datasheet(HTML) 85 Page - Exar Corporation |
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85 / 156 page  XRT86VL34 80 REV. V1.2.0 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION TABLE 60: PMON RECEIVE LINE CODE VIOLATION COUNTER MSB (RLCVCU) HEX ADDRESS: 0Xn900 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 RLCVC[15] RUR 0 Performance Monitor “Receive Line Code Violation” 16-bit Counter - Upper Byte: These RESET-upon-READ bits, along with that within the PMON Receive Line Code Violation Counter Register LSB combine to reflect the cumulative number of instances that Line Code Violation has been detected by the Receive T1 Framer block since the last read of this register. This register contains the Most Significant byte of this 16-bit of the Line Code Violation counter. NOTE: For all 16-bit wide PMON registers, user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts. To clear PMON count, user must read the MSB counter first before reading the LSB counter in order to clear the PMON count. 6 RLCVC[14] RUR 0 5 RLCVC[13] RUR 0 4 RLCVC[12] RUR 0 3 RLCVC[11] RUR 0 2 RLCVC[10] RUR 0 1 RLCVC[9] RUR 0 0 RLCVC[8] RUR 0 TABLE 61: PMON RECEIVE LINE CODE VIOLATION COUNTER LSB (RLCVCL) HEX ADDRESS: 0Xn901 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 RLCVC[7] RUR 0 Performance Monitor “Receive Line Code Violation” 16-bit Counter - Lower Byte: These RESET-upon-READ bits, along with that within the PMON Receive Line Code Violation Counter Register MSB combine to reflect the cumulative number of instances that Line Code Violation has been detected by the Receive T1 Framer block since the last read of this register. This register contains the Least Significant byte of this 16-bit of the Line Code Violation counter. NOTE: For all 16-bit wide PMON registers, user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts. To clear PMON count, user must read the MSB counter first before reading the LSB counter in order to clear the PMON count. 6 RLCVC[6] RUR 0 5 RLCVC[5] RUR 0 4 RLCVC[4] RUR 0 3 RLCVC[3] RUR 0 2 RLCVC[2] RUR 0 1 RLCVC[1] RUR 0 0 RLCVC[0] RUR 0 |
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