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XRT86VL34 Datasheet(PDF) 64 Page - Exar Corporation

Part # XRT86VL34
Description  QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
PDF  156 Pages
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT86VL34 Datasheet(HTML) 64 Page - Exar Corporation

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XRT86VL34
59
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
2
Tx_IDLE
R/W
0
Transmit Idle (Flag Sequence Byte)
This bit configures the Transmit HDLC Controller Block #2 to uncon-
ditionally transmit a repeating string of Flag Sequence octets (0X7E)
in the data link channel to the Remote terminal. In normal condi-
tions, the Transmit HDLC Controller block will repeatedly transmit
the Flag Sequence octet whenever there is no MOS message to
transmit to the remote terminal equipment. However, if the user
invokes this “Transmit Idle Sequence” feature, then the Transmit
HDLC Controller block will UNCONDITIONALLY transmit a repeat-
ing stream of the Flag Sequence octet (thereby overwriting all out-
bound MOS data-link messages).
0 - Configures the Transmit HDLC Controller Block # 2 to transmit
data-link information in a “normal” manner.
1 - Configures the Transmit HDLC Controller block # 2 to transmit a
repeating string of Flag Sequence Octets (0x7E).
NOTE:
This bit is ignored if the Transmit HDLC2 controller is
operating in the BOS Mode - bit 0 (MOS/BOS) within this
register is set to 0.
1
Tx_FCS_EN
R/W
0
Transmit LAPD Message with Frame Check Sequence (FCS)
This bit permits the user to configure the Transmit HDLC Controller
block # 2 to compute and append FCS octets to the “back-end” of
each outbound MOS data-link message.
0 - Configures the Transmit HDLC Controller block # 2 to NOT com-
pute and append the FCS octets to the back-end of each outbound
MOS data-link message.
1 - Configures the Transmit HDLC Controller block # 2 TO COM-
PUTE and append the FCS octets to the back-end of each outbound
MOS data-link message.
NOTE: This bit is ignored if the transmit HDLC2 controller has been
configured to operate in the BOS mode - bit 0 (MOS/BOS)
within this register is set to 0.
0
MOS/BOS
R/W
0
Message Oriented Signaling/Bit Oriented Signaling Send
This bit permits the user to enable LAPD transmission through
HDLC Controller Block # 2 using either BOS (Bit-Oriented Signaling)
or MOS (Message-Oriented Signaling) frames.
0 - Transmit HDLC Controller block # 2 BOS message Send.
1 - Transmit HDLC Controller block # 2 MOS message Send.
NOTE: This is not an Enable bit. This bit must be set to "0" each
time a BOS is to be sent.
TABLE 42: DATA LINK CONTROL REGISTER (DLCR2)
HEX ADDRESS: 0Xn143
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION



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