XRT86VL34 datasheet(96/156 Pages) EXAR

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XRT86VL34

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. V1.2.0

SLIP_ENB

R/W

Slip Buffer Block Interrupt Enable

This bit permits the user to either enable or disable the Slip Buffer

Block for interrupt generation.

Writing a “0” to this register bit will disable the Slip Buffer Block for

interrupt generation, then all Slip Buffer interrupts will be disabled for

interrupt generation.

If the user writes a “1” to this register bit, the Slip Buffer Block inter-

rupt at the “Block Level” will be enabled. However, the individual Slip

Buffer interrupts at the “Source Level” still need to be enabled in

order to generate that particular interrupt to the interrupt pin.

0 - Disables all Slip Buffer Block interrupt within the device.

1 - Enables the Slip Buffer interrupt at the “Block-Level”.

ALARM_ENB

R/W

Alarm & Error Block Interrupt Enable

This bit permits the user to either enable or disable the Alarm &

Error Block for interrupt generation.

Writing a “0” to this register bit will disable the Alarm & Error Block

for interrupt generation, then all Alarm & Error interrupts will be dis-

abled for interrupt generation.

If the user writes a “1” to this register bit, the Alarm & Error Block

interrupt at the “Block Level” will be enabled. However, the individual

Alarm & Error interrupts at the “Source Level” still need to be

enabled in order to generate that particular interrupt to the interrupt

pin.

0 - Disables all Alarm & Error Block interrupt within the device.

1 - Enables the Alarm & Error interrupt at the “Block-Level”.

T1FRAME_ENB

R/W

T1 Framer Block Enable

This bit permits the user to either enable or disable the T1 Framer

Block for interrupt generation.

Writing a “0” to this register bit will disable the T1 Framer Block for

interrupt generation, then all T1 Framer interrupts will be disabled

for interrupt generation.

If the user writes a “1” to this register bit, the T1 Framer Block inter-

rupt at the “Block Level” will be enabled. However, the individual T1

Framer interrupts at the “Source Level” still need to be enabled in

order to generate that particular interrupt to the interrupt pin.

0 - Disables all T1 Framer Block interrupt within the device.

1 - Enables the T1 Framer interrupt at the “Block-Level”.

TABLE 79: BLOCK INTERRUPT ENABLE REGISTER (BIER)

HEX ADDRESS: 0XnB01

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

XRT86VL34 Datasheet(PDF) 96 Page - Exar Corporation

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