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TMS320DM355 Datasheet(PDF) 42 Page - Texas Instruments |
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TMS320DM355 Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 153 page  www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463 – SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Pin BGA Type Grou Power PU Reset Description(4) Mux Control # ID (1) p Supply(2) PD(3 State ) DDR_CLK 59 W8 I/O DDR VDD_DDR out H DDR Complementary Data Clock DDR_RAS 60 T6 I/O DDR VDD_DDR out H DDR Row Address Strobe DDR_CAS 61 V9 I/O DDR VDD_DDR out H DDR Column Address Strobe DDR_WE 62 W10 I/O DDR VDD_DDR out H DDR Write Enable (active low) DDR_CS 63 T8 I/O DDR VDD_DDR out H DDR Chip Select (active low) DDR_CKE 64 V10 I/O DDR VDD_DDR out L DDR Clock Enable DDR_DQM[1] 65 U15 I/O DDR VDD_DDR out L Data mask outputs: DQM0: For DDR_DQ[7:0] DDR_DQM[0] 66 T12 I/O DDR VDD_DDR out L Data mask outputs: DQM1: For DDR_DQ[15:8] DDR_DQS[1] 67 V15 I/O DDR VDD_DDR in Data strobe input/outputs for each byte of the 16 bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading. DQS1: For DDR_DQ[15:8] DDR_DQS[0] 68 V12 I/O DDR VDD_DDR in Data strobe input/outputs for each byte of the 16 bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading. DQS0: For DDR_DQ[7:0] DDR_BA[2] 69 V8 I/O DDR VDD_DDR out L Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[1] 70 U7 I/O DDR VDD_DDR out L Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[0] 71 U8 I/O DDR VDD_DDR out L Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_A13 72 U6 I/O DDR VDD_DDR out L DDR Address Bus bit 13 DDR_A12 73 V7 I/O DDR VDD_DDR out L DDR Address Bus bit 12 DDR_A11 74 W7 I/O DDR VDD_DDR out L DDR Address Bus bit 11 DDR_A10 75 V6 I/O DDR VDD_DDR out L DDR Address Bus bit 10 DDR_A09 76 W6 I/O DDR VDD_DDR out L DDR Address Bus bit 09 DDR_A08 77 W5 I/O DDR VDD_DDR out L DDR Address Bus bit 08 DDR_A07 78 V5 I/O DDR VDD_DDR out L DDR Address Bus bit 07 DDR_A06 79 U5 I/O DDR VDD_DDR out L DDR Address Bus bit 06 DDR_A05 80 W4 I/O DDR VDD_DDR out L DDR Address Bus bit 05 DDR_A04 81 V4 I/O DDR VDD_DDR out L DDR Address Bus bit 04 DDR_A03 82 W3 I/O DDR VDD_DDR out L DDR Address Bus bit 03 DDR_A02 83 W2 I/O DDR VDD_DDR out L DDR Address Bus bit 02 DDR_A01 84 V3 I/O DDR VDD_DDR out L DDR Address Bus bit 01 DDR_A00 85 V2 I/O DDR VDD_DDR out L DDR Address Bus bit 00 DDR_DQ15 86 W17 I/O DDR VDD_DDR in DDR Data Bus bit 15 DDR_DQ14 87 V16 I/O DDR VDD_DDR in DDR Data Bus bit 14 DDR_DQ13 88 W16 I/O DDR VDD_DDR in DDR Data Bus bit 13 DDR_DQ12 89 U16 I/O DDR VDD_DDR in DDR Data Bus bit 12 DDR_DQ11 90 W15 I/O DDR VDD_DDR in DDR Data Bus bit 11 DDR_DQ10 91 W14 I/O DDR VDD_DDR in DDR Data Bus bit 10 DDR_DQ09 92 V14 I/O DDR VDD_DDR in DDR Data Bus bit 09 DDR_DQ08 93 U13 I/O DDR VDD_DDR in DDR Data Bus bit 08 DDR_DQ07 94 W13 I/O DDR VDD_DDR in DDR Data Bus bit 07 Device Overview 42 Submit Documentation Feedback |
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