TMS320DM355 datasheet(43/153 Pages) TI

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

Table 2-23. DM355 Pin Descriptions (continued)

Name

BGA

Type

Grou

Power

Reset

Description(4)

Mux Control

(1)

Supply(2)

PD(3

State

)

DDR_DQ06

V13

I/O

DDR

VDD_DDR

DDR Data Bus bit 06

DDR_DQ05

W12

I/O

DDR

VDD_DDR

DDR Data Bus bit 05

DDR_DQ04

U12

I/O

DDR

VDD_DDR

DDR Data Bus bit 04

DDR_DQ03

T11

I/O

DDR

VDD_DDR

DDR Data Bus bit 03

DDR_DQ02

U11

I/O

DDR

VDD_DDR

DDR Data Bus bit 02

DDR_DQ01

100

W11

I/O

DDR

VDD_DDR

DDR Data Bus bit 01

DDR_DQ00

101

V11

I/O

DDR

VDD_DDR

DDR Data Bus bit 00

DDR_GATE0

102

W18

I/O

DDR

VDD_DDR

DDR: Loopback signal for external DQS

gating. Route to DDR and back to

DDR_STRBEN_DEL with same

constraints as used for DDR clock and

data.

DDR_GATE1

103

V17

I/O

DDR

VDD_DDR

DDR: Loopback signal for external DQS

gating. Route to DDR and back to

DDR_STRBEN with same constraints as

used for DDR clock and data.

DDR_VREF

104

U10

PWR DDRI

VDD_DDR

DDR: Voltage input for the SSTL_18 IO

buffers

DDR_VSSDLL

105

R11

GND DDRD

VDD_DDR

DDR: Ground for the DDR DLL

DDR_VDDDLL

106

R10

PWR DDRD

VDD_DDR

DDR: Power (3.3 Volts) for the DDR DLL

DDR_ZN

107

I/O

DDRI

VDD_DDR

DDR: Reference output for drive strength

calibration of N and P channel outputs.

Tie to ground via 50 ohm resistor @

0.5% tolerance.

EM_A13 /

108

V19

I/O

AEMI

VDD

in L

Async EMIF: Address Bus bit[13]

PINMUX2[0].EM_A

GIO067 /

F /

13_3,

BTSEL[1]

GIO /

syste

GIO: GIO[067]

default set by

AECFG[0]

System: BTSEL[1:0] sampled at

Power-on-Reset to determine Boot

method (00:NAND, 01:Flash, 10:UART,

11:SD)

EM_A12 /

109

U19

I/O

AEMI

VDD

in L

Async EMIF: Address Bus bit[12]

PINMUX2[0].EM_A

GIO066 /

F /

13_3,

BTSEL[0]

GIO /

syste

GIO: GIO[066]

default set by

AECFG[0]

System: BTSEL[1:0] sampled at

Power-on-Reset to determine Boot

method (00:NAND, 01:Flash, 10:UART,

11:SD)

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