TMS320DM355 datasheet(80/153 Pages) TI

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3.11.2 PLL Configuration

3.11.3 Power Domain and Module State Configuration

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The

PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1

(typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3.5

and Section 3.6. The default state of the PLLs is reflected in the default state of the register bits in the

PLLC registers. Refer the the ARM Subsystem User's Guide for PLLC register descriptions.

Only a subset of modules are enabled after reset by default. Table 3-16 shows which modules are

enabled after reset. Table 3-16 as shows that the following modules are enabled depending on the

sampled state of the device configuration pins: EDMA (CC and TC0), AEMIF, MMC/SD0, UART0, and

Timer0. For example, UART0 is enabled after reset when the device configuration pins (BTSEL[1:0] = 11 -

Enable UART) select UART boot mode. For more information on module configuration refer to the ARM

Subsystem User's Guide.

Detailed Device Description

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TMS320DM355 Datasheet(PDF) 80 Page - Texas Instruments