TMS320DM355 datasheet(76/153 Pages) TI

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3.7 Power and Sleep Controller (PSC)

arm_clock

arm_mreset

arm_power

AINTC

ARM

module_power

module_mreset

MODx

module_clock

Alwayson

domain

Interrupt

PSC

clks

PLLC

Emulation

RESETN

VDD

DMSoC

3.8 System Control Module

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

In the DM355 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of

system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5. Many of

the operations of the PSC are transparent to software, such as power-on-reset operations. However, the

PSC provides you with an interface to control several important clock and reset operations.

The PSC includes the following features:

• Manages chip power-on/off, clock on/off, and resets

• Provides a software interface to:

–

Control module clock ON/OFF

–

Control module resets

• Supports IcePick emulation features: power, clock, and reset

For more information on the PSC, see the ARM Subsystem User's Guide.

Figure 3-5. DM355 Power and Sleep Controller (PSC)

The DM355’s system control module is a system-level module containing status and top-level control logic

required by the device. The system control module consists of a miscellaneous set of status and control

registers, accessible by the ARM and supporting all of the following system features and operations:

• Device identification

• Device configuration

–

Pin multiplexing control

–

Device boot configuration status

• ARM interrupt and EDMA event multiplexing control

• Special peripheral status and control

–

Timer64+

–

USB PHY control

–

VPSS clock and video DAC control and status

–

DDR VTP control

–

Clockout circuitry

–

GIO de-bounce control

Detailed Device Description

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