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TMS320DM355 Datasheet(PDF) 51 Page - Texas Instruments |
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TMS320DM355 Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 153 page ![]() www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463 – SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name Pin BGA Type Grou Power PU Reset Description(4) Mux Control # ID (1) p Supply(2) PD(3 State ) VSS_USB 186 B7 GND USBP VDD Analog 3.3 V ground for USB PHY HY (Transceiver) VDDA33_USB 187 C8 PWR USBP VDD Common mode 3.3 V power for USB _PLL HY PHY (PLL) VSS_USB 188 E6 GND USBP VDD Common mode 3.3 V ground for USB HY PHY (PLL) VDDA1P2_US 189 H7 PWR USBP VDD Analog 1.2 V power for USB PHY B HY VSS_USB 190 E6 GND USBP VDD Analog 1.2 V ground for USB PHY HY VDDD1P2_US 191 C6 PWR USBP VDD Digital 1.2 V power for USB PHY B HY VSS_USB 192 D6 GND USBP VDD Digital 1.2 V ground for USB PHY HY MMCSD0_CL 193 A15 I/O MMC VDD out L MMCSD0: Clock PINMUX4[2].MMC K SD0 SD0_MS MMCSD0_CM 194 C14 I/O MMC VDD in MMCSD0: Command PINMUX4[2].MMC D SD0 SD0_MS MMCSD0_DA 195 A14 I/O MMC VDD in MMCSD0: DATA3 PINMUX4[2].MMC TA3 SD0 SD0_MS MMCSD0_DA 196 B13 I/O MMC VDD in MMCSD0: DATA2 PINMUX4[2].MMC TA2 SD0 SD0_MS MMCSD0_DA 197 D14 I/O MMC VDD in MMCSD0: DATA1 PINMUX4[2].MMC TA1 SD0 SD0_MS MMCSD0_DA 198 B14 I/O MMC VDD in MMCSD0: DATA0 PINMUX4[2].MMC TA0 SD0 SD0_MS UART0_RXD 199 U18 I UART VDD in UART0: Receive Data 0 Used for UART boot mode UART0_TXD 200 T18 O UART VDD out H UART0: Transmit Data 0 Used for UART boot mode SPI0_SDENA[ 201 B12 I/O SPI0 / VDD in SPI0: Enable / Chip Select 0 PINMUX4[0].SPI0_ 0] / GIO103 GIO SDENA GIO: GIO[103] SPI0_SCLK 202 C12 I/O SPI0 VDD in SPI0: Clock SPI0_SDI / 203 A12 I/O SPI0 / VDD in SPI0: Data In PINMUX4[1].SPI0_ GIO102 GIO SDI GIO: GIO[102] SPI0_SDO 204 B11 I/O SPI0 VDD in SPI0: Data Out ASP1_DX 205 C18 I/O ASP5 VDD in ASP1: Transmit Data 121 ASP1_CLKX 206 D19 I/O ASP5 VDD in ASP1: Transmit Clock 121 ASP1_FSX 207 E16 I/O ASP5 VDD in ASP1: Transmit Frame Sync 121 ASP1_DR 208 C19 I/O ASP5 VDD in ASP1: Receive Data 121 ASP1_CLKR 209 D18 I/O ASP5 VDD in ASP1: Receive Clock 121 ASP1_FSR 210 E17 I/O ASP5 VDD in ASP1: Receive Frame Synch 121 Submit Documentation Feedback Device Overview 51 |
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