TMS320DM355 datasheet(93/153 Pages) TI

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Peripheral Information and Electrical Specifications

5.1

Parameter Information Device-Specific Information

TransmissionLine

4.0pF

1.85pF

Z0=50 Ω

(seenote)

Tester PinElectronics

Data SheetTimingReferencePoint

Output

Under

Test

42 Ω

3.5nH

DevicePin

(seenote)

5.1.1

Signal Transition Levels

Vref

Vref =VIL MAX(orVOL MAX)

Vref =VIH MIN(orVOH MIN)

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to

produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to

add

subtract

the

transmission

line

delay

longer)

from

the

data

sheet

timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the

device pin.

Figure 5-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,

Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.

Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,

VOLMAX and VOH MIN for output clocks.

Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels

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Peripheral Information and Electrical Specifications

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