STAC9767 datasheet(22/97 Pages) IDT

22 / 97 page

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

PC AUDIO

IDT™

STAC9766/9767

V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

The beginning of all audio sample packets, or Audio Frames, transferred over AC-link is synchro-

nized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller gener-

ates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This

yields a 48 KHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-link

on every rising edge of BIT_CLK, and subsequently sampled by the receiving device on the receiv-

ing side of AC-link on each immediately following falling edge of BIT_CLK.

4.3.

Controller to Multiple CODECs

Several vendor specific methods of supporting multiple CODEC configurations on AC-link have

been implemented or proposed, including CODECs with selective AC-link pass-through and control-

lers with duplicate AC-links.

Potential implementations include:

•

6-channel audio using 3 x 2-channel CODECs.

•

Separate CODECs for independent audio and modem AFE.

•

Docking stations, where one CODEC is in the laptop and another is in the dock.

This specification defines support for up to four CODECs on the AC-link. By definition there can be

one Primary CODEC (ID 00) and up to three Secondary CODECs (IDs 01,10, and 11). The CODEC

ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets;

each is individually accessible and they do not share registers.

Multiple CODEC AC-link implementations must run off a common BIT_CLK. They can potentially

save Controller pins by sharing SYNC, SDATA_OUT, and RESET# from the AC‘97 Digital Control-

ler. Each device requires its own SDATA_IN pin back to the Controller. This prevents contention of

multiple devices on one serial input line.

Support for multiple CODEC operation necessitates a specially designed Controller. An AC‘97 Digi-

tal Controller that supports multiple CODEC configurations implements multiple SDATA_IN inputs,

supporting one Primary CODEC and up to three Secondary CODECs.

4.3.1.

Primary CODEC Addressing

Primary AC‘97 CODECs respond to register read and write commands directed to CODEC ID 00.

Primary devices must be configurable (by hardwiring, strap pin(s), or other methods) as CODEC ID

00, and reflect this in the two-bit CODEC ID field(s) of the Extended Audio and/or Extended Modem

ID Register(s).

The Primary CODEC may either drive the BIT_CLK signal or consume a BIT_CLK signal provided

by the digital controller or other clock generator.

4.3.2.

Secondary CODEC Addressing

Secondary AC‘97 CODECs respond to register read and write commands directed to CODEC IDs

01, 10, or 11. Secondary devices must be configurable (via hardwiring, strap pin(s), or other meth-

ods) as CODEC IDs 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended

Modem ID Register(s).

STAC9767 Datasheet(PDF) 22 Page - Integrated Device Technology

STAC9767 Datasheet(HTML) 22 Page - Integrated Device Technology

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