STAC9767 datasheet(31/97 Pages) IDT

31 / 97 page

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

PC AUDIO

IDT™

STAC9766/9767

V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

5.3.

AC-link Output Frame (SDATA_OUT)

The AC-link output frame data streams correspond to the multiplexed bundles of all digital output

data targeting AC‘97’s DAC inputs, and control registers. As mentioned earlier, each AC-link output

frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot

containing 16-bits which are used for AC-link protocol infrastructure.

Figure 15 illustrates the time slot based AC-link protocol.

Figure 15. AC-Link Audio Output Frame

A new AC-link output frame begins with a low to high transition of SYNC. SYNC is synchronous to

the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97

CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-

troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-

tion is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97

CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 16. Start of an Audio Output Frame

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions

stuffed with 0 by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and valid

time slot, the AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0.

As an example, consider an 8-bit sample stream that is being played out to one of the STAC9766/

9767 DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next

SYNC

BIT_CLK

SDATA_OUT

slot1

slot2

End of previous audio frame

slot(12)

"0"

Data Phase

20.8 uS (48 kHZ)

Tag Phase

12.288 MHz

Time Slot "Valid" Bits

Slot 1

Slot 2

Slot 3

Slot 12

("1" = time slot contains valid PCM data)

CID1

CID0

valid

"0"

Frame

"0"

SYNC

BIT_CLK

SDATA_OUT

slot1

slot2

End of previous audio frame

valid

Frame

SYNC

asserted

first

SDATA_OUT

bit of frame

SYNC

detected by

codec

STAC9767 Datasheet(PDF) 31 Page - Integrated Device Technology

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