PM5351 datasheet(39/393 Pages) PMC

39 / 393 page

S/UNI-TETRA

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

DATASHEET

PMC-1971240

ISSUE 7

SATURN USER NETWORK INTERFACE (155-TETRA)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PIN DESCRIPTION

9.1

Line Side Interface Signals

Pin Name

Type

No.

Function

REFCLK

Input

AC5

The reference clock input (REFCLK) must provide a

jitter-free 19.44 MHz reference clock. It is used as

the reference clock by both clock recovery and

clock synthesis circuits.

When the WAN Synchronization controller is used,

REFCLK is supplied using a VCXO. In this

application, the transmit direction can be looped

timed to any of the line receivers in order to meet

wander transfer and holdover requirements.

This pin is shared by all channels.

RXD1+

RXD1-

RXD2+

RXD2-

RXD3+

RXD3-

RXD4+

RXD4-

Differential

PECL

inputs

AA1

The receive differential data inputs (RXD+, RXD-)

contain the NRZ bit serial receive stream. The

receive clock is recovered from the RXD+/- bit

stream. Please refer to the Operation section for a

discussion of PECL interfacing issues and for the

PECL voltage level selection through PECLV for 5V

ODL interface.

This pin is available independently for each

channel.

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