PM5351 datasheet(79/393 Pages) PMC

79 / 393 page

S/UNI-TETRA

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

DATASHEET

PMC-1971240

ISSUE 7

SATURN USER NETWORK INTERFACE (155-TETRA)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

The B2 error events counters optionally can be configured to accumulate only

"word" errors. A B2 word error is defined as the occurrence of one or more B2 bit

error events during a frame. The B2 error counter is incremented by one for each

frame in which a B2 word error occurs.

In addition the FEBE events counters optionally can be configured to accumulate

only "word" events. In STS-3c (STM-1) framing a FEBE word event is defined as

the occurrence of one or more FEBE bit events during a frame. The FEBE event

counter is incremented by one for each frame in which a FEBE event occurs.

10.4 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE)

10.4.1 Automatic Protection Switch Control

The Automatic Protection Switch (APS) control block filters and captures the

receive automatic protection switch channel bytes (K1 and K2) allowing them to

be read via the RASE APS K1 Register and the RASE APS K2 Register. The

bytes are filtered for three frames before being written to these registers. A

protection switching byte failure alarm is declared when twelve successive

frames have been received, where no three consecutive frames contain identical

K1 bytes. The protection switching byte failure alarm is removed upon detection

of three consecutive frames containing identical K1 bytes. The detection of

invalid APS codes is done in software by polling the RASE APS K1 Register and

the RASE APS K2 Register.

10.4.2 Bit Error Rate Monitor

The Bit Error Monitor Block (BERM) calculates the received line BIP-24 error

detection code (B2) based on the line overhead and synchronous payload

envelope of the receive data stream. The line BIP-24 code is a bit interleaved

parity calculation using even parity. Details are provided in the references. The

calculated BIP code is compared with the BIP-24 code extracted from the B2

byte(s) of the following frame. Any differences indicate that a line layer bit error

has occurred. Up to 192000 (24 BIP/frame x 8000 frames/second) bit errors can

be detected per second for STS-3c (STM-1) rate.

The BERM accumulates these line layer bit errors in a 20 bit saturating counter

that can be read via the microprocessor interface. During a read, the counter

value is latched and the counter is reset to 0 (or 1, if there is an outstanding

event). Note, this counter should be polled at least once per second to avoid

saturation which in turn may result in missed bit error events.

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