PM5351 datasheet(40/393 Pages) PMC

40 / 393 page

S/UNI-TETRA

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

DATASHEET

PMC-1971240

ISSUE 7

SATURN USER NETWORK INTERFACE (155-TETRA)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

SD1

SD2

SD3

SD4

Single-

Ended

PECL

Input

The Signal Detect pin (SD) indicates the presence

of valid receive signal power from the Optical

Physical Medium Dependent Device. A PECL high

indicates the presence of valid data and a PECL low

indicates a loss of signal. It is mandatory that SD be

terminated into the equivalent network that RXD+/-

is terminated into.

SD input is compared to the common mode of the

receive data line (RXD+/-). It is also assumed SD

will be driven by a low impedance PECL voltage

source coming from the same source as the RXD+/-

signals

This pin is available independently for each

channel.

RCLK1

RCLK2

RCLK3

RCLK4

Output

AA13

Y13

AC14

AB14

The receive byte clock (RCLK) provides a timing

reference for the S/UNI-TETRA receive outputs.

RCLK is a divide by eight of the recovered line rate

clock (19.44 MHz).

This pin is available independently for each

channel.

RFPO1

RFPO2

RFPO3

RFPO4

Output

AA12

AB12

AC13

AB13

The Receive Frame Pulse Output (RFPO), when

the framing alignment is found (the OOF register bit

is logic zero), is an 8 kHz signal derived from the

receive line clock. RFPO pulses high for one RCLK

cycle every 2430 RCLK cycles (STS-3c (STM-1)).

RFPO is updated on the rising edge of RCLK.

This pin is available independently for each

channel.

PM5351 Datasheet(PDF) 40 Page - PMC-Sierra, Inc

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