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PM5351 Datasheet(PDF) 43 Page - PMC-Sierra, Inc |
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PM5351 Datasheet(HTML) 43 Page - PMC-Sierra, Inc |
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43 / 393 page ![]() S/UNI-TETRA PMC-Sierra, Inc. PM5351 S/UNI-TETRA DATASHEET PMC-1971240 ISSUE 7 SATURN USER NETWORK INTERFACE (155-TETRA) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23 Pin Name Type Pin No. Function TFPO Output AB11 The Transmit Frame Pulse Output (TFPO) pulses high for one TCLK cycle every 2430 TCLK cycles and provides an 8 KHz timing reference. TFPO can be assigned to any of the four channels using TFPO_CH[1:0] configuration register bits, with the restriction that the selected channel must be self- timed (not in loop-timed or line-loopback modes). TFPO is updated on the rising edge of TCLK. 9.2 Section and Line Status DCC Signals Pin Name Type Pin No. Function RSD1 RSD2 RSD3 RSD4 Output AB17 Y16 AA17 AB18 The receive section DCC (RSD) signal contains the section data communications channel (D1-D3) This pin is available independently for each channel. RSDCLK1 RSDCLK2 RSDCLK3 RSDCLK4 Output AC20 AA19 AB20 AC21 The receive section DCC clock (RSDCLK) is used to clock out the section DCC. RSDCLK is a 192 kHz clock used to update the RSD output. RSDCLK is generated by gapping a 216 kHz clock. This pin is available independently for each channel. TSD1 TSD2 TSD3 TSD4 Input AB6 AA7 Y8 AB7 The transmit section DCC (TSD) signal contains the section data communications channel (D1-D3). TSD is sampled on the rising edge of TSDCLK. This pin is available independently for each channel. |
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