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TMPR4937 Datasheet(PDF) 359 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 359 Page - Toshiba Semiconductor

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Chapter 10 PCI Controller
10-101
10.5.3 Power Management Capability Register (PMC) 0xDE
15
11
10
9
8
6
5
4
3
2
0
PMESPT
D2SPT D1SPT
Reserved
DSI Reserved PMECLK
PMVER
R
R
R
R
R
R
: Type
0x19
0
0
0
0
0x2
: Initial value
Bit
Mnemonic
Field Name
Description
Read/Write
15:11
PMESPT
PME Output
Support
PME_ Support (Fixed Value: 0x09)
Indicates that the PME* signal can be output from the state where the bit is
set to “1”.
Bit 15: Can output the PME* signal from the D3cold state.
Bit 14: Can output the PME* signal from the D3hot state.
Bit 13: Can output the PME* signal from the D2 state.
Bit 12: Can output the PME* signal from the D1 state.
Bit 11: Can output the PME* signal from the D0 state.
Note:
With the TX4937 PCI Controller, it is possible to output the
PME* signal from the D0 and the D3hot states.
R
10
D2SPT
D2 Support
D2_Support (Fixed Value: 0)
0: Indicates that the D2 state is not supported.
R
9
D1SPT
D1 Support
D1_Support (Fixed Value: 0)
0: Indicates that the D1 state is not supported.
R
8:6
Reserved
⎯
5
DSI
DSI
DSI (Fixed Value: 0)
0: Indicates that Device Specific Initialization is not required.
R
4
Reserved
⎯
3
PMECLK
PME Clock
PME Clock (Fixed Value: 0)
0: Indicates that the PCI Clock is not required to assert the PME* signal.
R
2:0
PMVER
Power
Management I/F
Version
Version (Fixed Value: 0x2)
2: Indicates compliance with "PCI Power Management Interface
Specification" Version 1.1.
R
Figure 10.5.3 PMC Register



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