TMPR4937 datasheet(89/552 Pages) TOSHIBA

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Chapter 5 Configuration Registers

5-9

Bit

Mnemonic

Field Name

Description

Initial Value Read/Write

SEL1

Shared-Pin

Status 1

Indicates which function, PIO[15:8] or CB[7:0], the shared pins

are set to.

L: 0 = The shared pins are set to PIO[15:8].

H: 1 = The shared pins are set to CB[7:0].

ADDR[18]

7:4

⎯

Reserved

⎯

DMASEL3

DMA Request

Select 3

Selects a DMA request used by DMA controller 0 channel 3.

0: DMAREQ[3] (external)

1: SIO channel 0 transmission (internal)

R/W

DMASEL2

DMA Request

Select 2

Selects a DMA request used by DMA controller 0 channel 2.

0: DMAREQ[2] (external)

1: SIO channel 0 reception (internal)

R/W

DMASEL1

DMA Request

Select 1

Selects a DMA request used by DMA controller 0 channel 1.

00: DMAREQ[1] (external)

01: SIO channel 1 transmission (internal)

R/W

1:0

DMASEL0

DMA Request

Select 0

Selects a DMA request used by DMA controller 0 channel 0.

00: DMAREQ[0] (external)

01: SIO channel 1 reception (internal)

R/W

Figure 5.2.3 Pin Configuration Register (3/3)

TMPR4937 Datasheet(PDF) 89 Page - Toshiba Semiconductor

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