TMPR4937 datasheet(501/552 Pages) TOSHIBA

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Chapter 20 Extended EJTAG Interface

20-3

20.2.2 Instruction Register

The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting

either one or both of the test to be performed and the Test Data Register to be accessed. The Data

RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for more information regarding each

instruction.

Table 20.2.1 Bit Configuration of JTAG Instruction Register

Instruction Code

MSB

→ LSB

Instruction

Selected Data Register

00000000 (0x00)

EXTEST

Boundary Scan Register

00000001 (0x01)

SAMPLE/PRELOAD

Boundary Scan Register

00000010 (0x02)

Reserved

00000011 (0x03)

IDCODE

Device ID Register

00000100 - 00001111

Reserved

00010000 (0x10)

HIGHZ

Bypass Register

00010001 - 01111111

Reserved

10000000 - 11111110

Refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture”

11111111 (0xFF)

BYPASS

Bypass Register

Figure 20.2.1 shows the format of the Instruction Register.

MSB

LSB

Figure 20.2.1 Instruction Register

The instruction code is shifted to the Instruction Register starting from the Least Significant Bit.

LSB

TDO

TDI

MSB

Figure 20.2.2 Shift Direction of the Instruction Register

20.2.3 Boundary Scan Register

The Boundary Scan Register contains a single 391-bit shift register to which all TX4937 I/O signals

except for power supply, TDI, TCK, TDO, TMS, TRST*, and TEST[4]* are connected. Figure 20.2.3 shows

the bits of the Boundary Scan Register.

390

Refer to TX4937 BSDL file

Figure 20.2.3 Boundary Scan Register

TDI input is fetched to the Most Significant Bit (MSB) of the Boundary Scan Register and the Least

Significant Bit (LSB) of the Boundary Scan Register is sent from the TDO output.

Table 20.2.2 shows the boundary scan sequence relative to the processor signals.

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