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TMPR4937 Datasheet(PDF) 242 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 242 Page - Toshiba Semiconductor |
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242 / 552 page ![]() Chapter 9 SDRAM Controller 9-26 9.5 Timing Diagrams Please note the following when referring to the timing diagrams in this section: the shaded area in each diagram expresses values that have yet to be determined. 9.5.1 Single Read (64-bit Bus) Figure 9.5.1 Single Read (tRCD = 2, tCASL = 2, tDA = 0, 64-bit Bus) DATA [63:0] CB [7:0] 00 ff ff SDCLK SDCS* ADDR [19:5] RAS* CAS* WE* CKE DQM [7:0] ACK*/READY* 7fff 0000 |
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