TMPR4937 datasheet(329/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-71

10.4.43 PCI Controller Configuration Register (PCICCFG)

0xD170

Reserved

GBWC

R/W

: Type

0xfff

: Initial value

Reserved

HRST SRST IRBER G2PM0EN G2PM1EN G2PM2EN G2PIOEN TCAR ICAEN LCFG

Reserved

R/W

: Type

0x0

0x1

0x0

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:28

Reserved

⎯

27:16

GBWC

G-Bus Wait

Counter Setting

G Bus Wait Counter (Default: 0xFFF)

Sets the Retry response counter at the G-Bus during a PCI initiator Read

transaction.

When the initiator Read access cycle exceeds the setting of this counter, a

Retry response is sent to the G-Bus and the G-Bus is released. PCI Read

operation continues. This counter uses the G-Bus clock (GBUSCLK) when

operating.

When 0x000 is set, a Retry response is not sent to the G-Bus by a long

response cycle count.

When the G-Bus timeout count is used with the value other than the initial

value 4096 GBUSCLK, G-BUS timeout may occur before a Retry response

is sent.

When G-Bus timeout of the configuration register (CCFG.GTOT) is used

with the value other than the initial value (11), set the following maximum

values to the register.

GTOT value

Maximum value of the register

10 (2048 GBUSCLK) : 0x7f0

01 (1024 GBUSCLK) : 0x3f0

00 ( 512 GBUSCLK) : 0x1f0

R/W

15:12

Reserved

⎯

HRST

Hardware Reset

Hard Reset (Default: 0x0)

Performs PCI Controller hardware reset control. EEPROM reloading is also

performed. This bit is automatically cleared when Reset ends. This is a

diagnostic function.

The PCI Controller cannot be accessed for 32 G-Bus clock cycles after this

bit is set.

1: Perform a hardware reset on the PCI Controller.

0: Do not perform a hardware reset on the PCI Controller.

R/W

Figure 10.4.41 PCI Controller Configuration Register (1/3)

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