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TMPR4956C Datasheet(PDF) 253 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 253 Page - Toshiba Semiconductor

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Chapter 15 CPU Instruction Set Summary
15-1
15. CPU Instruction Set Summary
15.1 Introduction
Each instruction is 32 bits long. These instructions are upward compatible with the MIPS I, II and III
instruction set architecture.
15.2 Instruction Format
There are three instruction formats: Immediate (I-type), Jump (J-type) and Register (R-type), as shown in
Figure 15.2.1. Having just three instruction formats simplifies instruction decoding. If more complex functions
or addressing modes are required, they can be produced with the compiler using combinations of the
instructions.
Immediate (I-type)
31
26
25
21
20
16
15
0
op
rs
rt
immediate
Jump (J-type)
31
26
25
0
op
target
Register (R-type)
31
26
25
21
20
16
15
11
10
6
5
0
op
rs
rt
rd
sa
funct
op
Operation code (6 bits)
rs
Source register (5 bits)
rt
Target (source or destination) register, or branch condition (5 bits)
rd
Destination register (5 bits)
immediate
Immediate, branch displacement, address displacement (16 bits)
target
Branch target address (26 bits)
sa
Shift amount (5 bits)
funct
Function (6 bits)
Figure 15.2.1 Instruction Formats and Subfield Mnemonics



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