13892 datasheet(65/158 Pages) FREESCALE

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FUNCTIONAL DEVICE OPERATION

OPERATING MODES

Analog Integrated Circuit Device Data



Freescale Semiconductor

MC13892

When requesting standby, a programmable delay (STBYDLY) of 0 to 3 clock cycles of the 32 kHz clock is applied before

actually going into standby (i.e. before turning off some supplies). No delay is applied when coming out of standby.

REGULATOR MODE CONTROL

The regulators with embedded pass devices (VDIG, VPLL, VIOHI, VUSB, VUSB2, and VAUDIO) have an adaptive biasing

scheme, thus, there are no distinct operating modes such as a Normal mode and a Low-power mode. Therefore, no specific

control is required to put these regulators in a Low-power mode.

The regulators with external pass devices (VSD, VVIDEO, VGEN1, and VGEN2) can also operate in a Normal and Low-power

mode. However, since a load current detection cannot be performed for these regulators, the transition between both modes is

not automatic and is controlled by setting the corresponding mode bits for the operational behavior desired.

The regulators VGEN3 and VCAM can be configured for using the internal pass device or external pass device as explained

in Power Control System. For both configurations, the transition between Normal and Low-power modes is controlled by setting

the VxMODE bit for the specific regulator. Therefore, depending on the configuration selected, the automatic Low-power mode

is available.

The regulators can be disabled and the general purpose outputs can be forced low when going into Standby as described

previously. Each regulator and GPO has an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The

actual operating mode of the regulators as a function of STANDBY is not reflected through the SPI. In other words, the SPI will

read back what is programmed, not the actual state.

For regulators with internal pass devices and general outputs, the previous table can be simplified.

Notes

58.

STANDBY = 0: System is not in Standby; STANDBY = 1: System is in Standby and Standby programmability is activated.

Table 31. Delay of STANDBY- Initiated Response

STBYDLY[1:0]

Function (1)

No Delay

One 32 K period (default)

Two 32 K periods

Three 32 K periods

Table 32. LDO Regulator Control (External Pass Device LDOs)

VxEN

VxMODE

VxSTBY

STANDBY

Regulator Vx

Off

Low-power

Off

Low-power

Notes

59.

This table is valid for regulators with an external pass device

60.

STANDBY refers to a Standby event as described earlier

Table 30. Standby Pin and Polarity Control

STANDBY (Pin)

STANDBYINV (SPI bit)

STANDBYSEC (Pin)

STANDBYSECINV (SPI bit)

STANDBY Control (58)

13892 Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc

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