13892 datasheet(81/158 Pages) FREESCALE

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FUNCTIONAL DEVICE OPERATION

SUPPLIES

Analog Integrated Circuit Device Data



Freescale Semiconductor

MC13892

Figure 22. SID Control Example for Panic Mode Recovery

The system will not respond to a new jog command until it has completed a DVS step that may be in progress. Any missed

jog requests will not be stored. For instance, if a switcher is stepping up in voltage with a 25 mV step over a 4.0

s time, response

to the DVSx pin for another step will be ignored until the DVS step period has expired. However, the Panic Mode step recovery

should respond immediately upon detection of the third SPICLK edge while the corresponding DVSx pin is high, even if the initial

decode of the jog up command is ignored, because it came in before the previous step was completed.

While in SID mode, programmable stops are used to set limits on how far up and how far down a SID-controlled buck regulator

will be allowed to step. The SWxSIDMIN[3:0] and SWxSIDMAX[3:0] bits can be used to ensure that voltage stepping is confined

to within the acceptable bounds for a given process technology used for the BB IC.

To contain all of the SWx voltage setting bits in single banks, the SWxSIDMIN[3:0] word is shortened to 4-bits, but should be

decoded by logic to have an implied leading 0 (i.e., MSB = 0, but is not included in the programmable word). For instance,

SW1SIDMIN = 1000 (default value) should be decoded as 01000, which corresponds to 0.800 V (assuming SW1HI = 0).

Likewise, the SWxSIDMAX[3:0] word is shortened to 4-bits, but should be decoded by logic to have an implied leading 1

(MSB = 1, but is not included in the programmable word). For instance, SW1SIDMAX = 1010 (default value) should be decoded

as 11010, which corresponds to 1.250 V (again, assuming SW1HI = 0).

A new SPI write for the active switcher output value with SWx[4:0] should take immediate effect, and this becomes the new

baseline from which succeeding SID steps are referenced. The SWxDVS[4:0] value is not considered during SID mode. The

system only uses the SWx[4:0] bits and the min/max stops SWxSIDMIN[3:0] and SWxSIDMAX[3:0].

When in SID mode, a STANDBY = 1 event (pin states of STANDBY and STANDBYSEC) will have the “immediate” effect (after

any STBYDLY delay has timed out) of changing the set point and mode to those defined for Standby operation. Exiting Standby

puts the system back to the normal mode set point with no stored SID adjustments -- the system will recalibrate itself again from

the refreshed baseline.

BOOST REGULATOR

SWBST is a boost switching regulator with a fixed 5.0 V output. It runs at 2/3 of the switcher PLL frequency. SWBST supplies

the VUSB regulator for the USB system in OTG mode, and it also supplies the power for the RGB LED's. When SWBST is

configured to supply the VBUS pin in OTG mode, the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB

pin. Therefore, when driving the VBUS for OTG mode the output of the switcher may rise to 5.75 V to compensate for the voltage

drops on the internal switches. Note that the parasitic leakage path for a boost regulator will cause the output voltage

SWBSTOUT and SWBSTFB to sit at a Schottky drop below the battery voltage whenever SWBST is disabled. The switching

NMOS transistor is integrated on-chip. An external fly back Schottky diode, inductor and capacitor are required.

SW1 output

DVS1

SPICLK

1.050

Starting Value DVS

SID Panic Mode Example

Panic

DVS step all the way back to 1.250V

(SW1[4:0] programmed value = 1.250V)

SPICLK shut down when not used

13892 Datasheet(PDF) 81 Page - Freescale Semiconductor, Inc

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