13892 datasheet(67/158 Pages) FREESCALE

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FUNCTIONAL DEVICE OPERATION

OPERATING MODES

Analog Integrated Circuit Device Data



Freescale Semiconductor

MC13892

POWER GATING SYSTEM

The Low-power Off states are provided to allow faster system booting from two pseudo Off conditions: Memory Hold, which

keeps the external memory powered for self refresh, and User Off, which keeps the processor powered up for state retention.

For reduced current drain in Low-power Off states, parts of the system can benefit from power gating to isolate the minimum

essentials for such operational modes. It is also necessary to ensure that the power budget on backed up domains are within the

capabilities of switchers in PFM mode. An additional benefit of power gating peripheral loads during system startup is to enable

the processor core to complete booting, and begin running software before additional supplies or peripheral devices are powered.

This allows system software to bring up the additional supplies and close power gating switches in the most optimum order, to

avoid problems with supply sequencing or transient current surges. The power gating switch drivers and integrated control are

included for optimizing the system power tree.

The power gate drivers could be used for other general power gating as well. The text herein assumes the standard application

of PWGT1 for core supply power gating and PWGT2 for Memory Hold power gating.

USER OFF POWER GATING

User Off configuration maintains PFM mode switchers on both the processor and external memory power domains.

PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/

or SW3. In addition, PWGTDRV2 is provided support to power gate peripheral loads on the SW4 supply domain.

In the typical application, SW1, SW2, and SW3 will all be kept active for the processor modules in state retention, and SW4

retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected

to PWGTDRV1 (for parallel NMOS switches); SW4 power gating FET drive would typically be connected to PWGTDRV2. When

Low-power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to

isolate the maintained supply domains from any peripheral loading.

The power gate switch driver consist of a fully integrated charge pump (~5.0 V) which provides a low-power output to drive

the gates of external NMOS switches placed between power sources and peripheral loading. The processor core(s) would

typically be connected directly to the SW1 output node so that it can be maintained by SW1, while any circuitry that is not essential

for booting or User Off operation is decoupled via the power gate switch. If multiple power domains are to be controlled together,

power gating NMOS switches can share the PWGT1 gate drive. However, extra gate capacitance may require additional time for

the charge pump gate drive voltage to reach its full value for minimum switch RDS_on.

Table 35. Switcher Control In Memory Hold

SWxMHMODE

Memory Hold Operational Mode (64)

Off

PFM

Notes

64.

For Memory Hold mode, an activated SWx should use the Standby set point as programmed

by SWxSTBY[4:0].

Table 36. Switcher Control In User Off

SWxUOMODE

User Off Operational Mode (65)

Off

PFM

Notes

65.

For User Off mode, an activated SWx should use the Standby set point as programmed by

SWxSTBY[4:0].

13892 Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc

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