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INA333 Datasheet(PDF) 7 Page - Texas Instruments |
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INA333 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 49 page  SCLK CS tSU_CSCK tHT_CKCS tDZ_CSDO SCLK SDI SDO tCLK tSU_CKDI tHT_CKDI tD_CKDO 7 PGA280 www.ti.com SBOS487B – JUNE 2009 – REVISED MARCH 2020 Product Folder Links: PGA280 Submit Documentation Feedback Copyright © 2009–2020, Texas Instruments Incorporated 6.3 Timing Requirements: Serial Interface at TA = –40°C to +105°C, DVDD = 2.7 V to 5.5 V, and CLOAD on SDO = 20 pF (unless otherwise specified) MIN NOM MAX UNIT fSCLK Serial clock frequency 16 MHz tCLK Serial clock time period 62.5 ns tSU_CSCK Setup time: CS falling to first SCLK capture (falling) edge 0 ns tHT_CKCS Delay time: last SCK capture (falling) to CS rising 0 ns tSU_CKDI Setup time: SDI data valid to SCLK capture (falling) edge 5 ns tHT_CKDI Hold time: SCLK capture (falling) edge to previous data valid on SDI 10 ns tDZ_CSDO Delay time: CS rising to SDO going to Hi-Z 25 ns tD_CKDO Delay time: SCLK rising edge to (next) data valid on SDO 25 ns Figure 1. Serial Timing Diagram |
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