INA701 datasheet(19/47 Pages) TI2

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Settings for the conversion time and number of conversions averaged impact the effective measurement

resolution. See ADC Output Data Rate and Noise Performance for more detailed information on how averaging

reduces noise and increases the effective number of bits (ENOB).

6.3.6 Integrated Precision Oscillator

The internal timebase of the device is provided by an internal oscillator that is trimmed to less than 0.5%

tolerance at room temperature. The precision oscillator is the timing source for ADC conversions, as well as

the time-count used for calculation of energy and charge. The digital filter response varies with conversion

time; therefore, the precise clock provides filter response and notch frequency consistency across temperature.

On power up, the internal oscillator and ADC take roughly 300µs to reach <1% error stability. After the clock

stabilizes, the ADC data output is accurate to the electrical specifications provided in Specifications.

6.3.7 Multi-Alert Monitoring and Fault Detection

The INA701 includes a multipurpose, open-drain, ALERT output pin that can be used to report multiple

diagnostics or as an indicator that the ADC conversion is complete when the device is operating in both

triggered and continuous conversion mode. The diagnostics listed in Table 6-1 are constantly monitored and can

be reported through the ALERT pin whenever the monitored output value crosses the associated out-of-range

threshold.

Table 6-1. ALERT Diagnostics Description

INA701 DIAGNOSTIC

STATUS BIT IN ALERT_DIAG REGISTER

(READ ONLY)

OUT-OF-RANGE

THRESHOLD

VALUE

Current Under-Limit

CURRENTUL

CUL

0x8000 h

(2's complement))

Current Over-Limit

CURRENTOL

COL

0x7FFF h

(2's complement))

Bus Voltage Over-Limit

BUSOL

BOVL

0x7FFF h

(2's complement), positive

values only)

Bus Voltage Under-Limit

BUSUL

BUVL

0x0000 h

(2's complement), positive

values only)

Temperature Over-Limit

TMPOL

TEMP_LIMIT

0xFFFF h

(2's complement), positive

values only)

Power Over-Limit

POL

PWR_LIMIT

0x7FFF h

(2's complement))

A read of the ALERT_DIAG register is used to determine which diagnostic triggered the ALERT pin. This

ALERT pin functions.

• Alert latch enable — In case the ALERT pin is triggered, this function holds the value of the pin even after all

diagnostic conditions have cleared. A read of the ALERT_DIAG register resets the status of the ALERT pin.

This function is enabled by setting the ALATCH bit.

• Conversion ready enable — Enables the ALERT pin to assert when an ADC conversion is complete and

output values are ready to be read through the digital interface. This function is enabled by setting the CNVR

bit. The conversion completed events can also be read through the CNVRF bit regardless of the CNVR bit

setting.

• Alert comparison on averaged output — Allows the out-of-range threshold value to be compared to the

averaged data values produced by the ADC. This helps remove noise from the output data when compared

to the out-of-range threshold to avoid false alerts due to noise. However, the diagnostic is delayed due to the

time needed for averaging. This function is enabled by setting the SLOWALERT bit.

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INA701

SBOSAM2 – AUGUST 2025

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