INA701 datasheet(39/47 Pages) TI2

39 / 47 page

8 Power Supply Recommendations

The input circuitry of the device can accurately measure signals on common-mode voltages beyond the power-

supply voltage, VS. For example, the voltage applied to the VS power supply terminal can be 5V, whereas the

load power-supply voltage being monitored (the common-mode voltage) can be as high as 40V. Note that the

device can also withstand the full 0V to 40V range at the input terminals, regardless of whether the device has

power applied or not. Avoid applications where the GND pin is disconnected while device is actively powered.

Place the required power-supply bypass capacitors as close as possible to the supply and ground terminals of

the device. A typical value for this supply bypass capacitor is 0.1µF. Applications with noisy or high-impedance

power supplies can require additional decoupling capacitors to reject power-supply noise.

9 Layout

9.1 Layout Guidelines

A layout that maximizes the thermal conduction from the IN– and IN+ pads is essential when sensing high load

currents. The area of the thermal planes connecting to these pads can be maximized, filling any available area,

while located as close as possible to the device. Thermal vias can be used generously and placed as close as

possible to the IN– and IN+ pads to maximize thermal conduction to the bottom and available internal layers.

To achieve better thermal performance, both the bottom and available internal layers can be used to conduct

the heat away from the device. See the INA701EVM User's Guide for more information on via and power plane

placement in a multilayer design. Place the power-supply bypass capacitor as close as possible to the supply

and ground pins.

9.2 Layout Example

IN+

IN–

SDA

ADR

GND

SCL

ALERT

2C Bus Connections

ALERT, SDA, and SCL require external

pull-up resistors to the digital supply

voltage. The layout of these resistors

have been omitted and are not as

critical to the device performance.

CBYPASS

Supply Voltage

2.7V to 5.5V

VIA to GND plane

Thermal Vias to bottom and internal

layers for device heat sinking

Device address pin must be connected

to either GND, SCL, SDA, or VS to

select the desired address.

Connect to VBUS for

high-side sensing or to

ground side of the load

for low side sensing

Connect to supply side of

the load for high-side

sensing or to ground for

low side sensing

Figure 9-1. INA701 Layout Example

www.ti.com

INA701

SBOSAM2 – AUGUST 2025

Submit Document Feedback

Product Folder Links: INA701

INA701 Datasheet(PDF) 39 Page - Texas Instruments

INA701 Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL