INA701 datasheet(22/47 Pages) TI2

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6.5 Programming

6.5.1 I2C Serial Interface

The INA701 operates only as a secondary device on both the SMBus and I2C interfaces. Connections to the

bus are made through the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike

suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the

device integrates spike suppression into the digital I/O lines, proper layout techniques help minimize the amount

of coupling into the communication lines. This noise introduction occurs from capacitive coupling signal edges

between the two communication lines themselves or from other switching noise sources present in the system.

Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the

effects of coupling between the communication lines. Shielded communication lines reduce the possibility of

incorrectly interpreting unintended noise coupling into the digital I/O lines as start or stop commands.

The INA701 supports the transmission protocol for fast mode (1kHz to 400kHz) and high-speed mode (1kHz

to 2.94MHz). All data bytes are transmitted most significant byte (MSB) first and follow the SMBus 3.0 transfer

protocol.

To communicate with the INA701, the main device must first address secondary devices through a secondary

device address byte. The secondary device address byte consists of seven address bits and a direction bit that

indicates whether the action is to be a read or write operation.

The device has a single address pin, A0. Table 6-2 lists the pin logic levels for each of the four possible

addresses. The device samples the state of the address pin on every bus communication. Establish the pin

states before any activity on the interface occurs.

Table 6-2. Address Pins and Secondary Device Addresses

DEVICE ADDRESS

GND

1010100

1010101

SDA

1010110

SCL

1010111

Note

When connecting the A0 pin to SDA to set the device address, an additional hold time of 100ns is

needed on the MSB of the I2C address to provide correct device addressing.

6.5.1.1 Writing to and Reading Through the I2C Serial Interface

Accessing a specific register on the INA701 is accomplished by writing the appropriate value to the register

pointer. See Register Maps for a complete list of registers and corresponding addresses. The value for the

with the R/W bit low. Every write operation to the device requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the main device. This byte is the secondary

device address, with the R/W bit low. The device then acknowledges receipt of a valid address. The next

byte transmitted by the main device is the address of the register to be accessed. This register address value

updates the register pointer to the desired internal device register. The next two bytes are written to the register

addressed by the register pointer. The device acknowledges receipt of each data byte. The main device can end

data transfer by generating a start or stop condition.

When reading from the device, the last value stored in the register pointer by a write operation determines which

be written to the register pointer. This write is accomplished by issuing a secondary device address byte with

the R/W bit low, followed by the register pointer byte. No additional data are required. The main device then

generates a start condition and sends the address byte for the secondary device with the R/W bit high to initiate

the read command. The next byte is transmitted by the secondary device and is the most significant byte of the

INA701

SBOSAM2 – AUGUST 2025

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