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AMC7834 Datasheet(PDF) 39 Page - Texas Instruments

Part # AMC7834
Description  AMC7834 12-Bit Integrated Power-Amplifier Monitor and Control System with Temperature, Current and Voltage Supervision Capabilities
PDF  97 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

AMC7834 Datasheet(HTML) 39 Page - Texas Instruments

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PA Controller
V(DRAIN)
RF Out
DAC
RF In
HPA
V(BIAS)
PA_ON
Control
PA_ON
PAVDD
PMOS Switch
39
AMC7834
www.ti.com
SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016
Product Folder Links: AMC7834
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Copyright © 2014–2016, Texas Instruments Incorporated
7.3.5 Drain Switch Control
The AMC7834 device includes an output-control voltage (PA_ON pin) capable of driving an external PMOS
switch that turns on and off the drain current to a PA FET. The use of this control signal in conjunction with the
DAC clamp option allows control of the sequence in which the PA FET is powered up and powered down.
The OFF and ON states of the PA_ON signal are equal to the PAVDD and AGND pins, respectively. The default
state of the PA_ON signal is off (PMOS switch off).
Figure 53. PA_ON Operation
The maximum output voltage is determined by the PAVDD pin and limited to a maximum of 20 V. For PA FETs
with drain voltages higher than 20 V, tying the PAVDD pin to one of the other supply devices (preferably AVDD)
and scaling the control signal externally is recommended.
The PA_ON signal state can be set through a register write, but it can also be configured to be triggered
automatically by the ALARMOUT pin, any of the SLEEP signals or by the special AVSS and AVDD monitoring
circuits.
For FETs requiring a negative bias voltage, such as GaN, ensuring that the bias voltage remains within an
acceptable range is crucial otherwise significant and irreversible damage to the FET can occur. The AMC7834
bipolar DAC operation and clamping mechanism rely on the AVDD and AVSS voltages for proper operation. For
this reason, when either the AVDD or AVSS voltage falls outside its acceptable range, turning off the drain current
to the FET is desirable.
The AVDD detection circuit is set to trigger the PA_ON signal to the OFF state in response to an out of range
event. Additionally, the AVSS detection alarm can be set to trigger the PA_ON signal to the OFF state by setting
the PAON_AVSS bit to 1 in the AMC configuration 1 register (address 0x11). The AVSS alarm is set by default to
prevent the PA_ON output from entering the ON state (PMOS switch on). In this case writing to the PA_ON
register bit to enable the ON state is ignored. If this additional protection is not needed it can be disabled by
clearing the PAON_AVSS bit.



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