AMC7834 datasheet(13/97 Pages) TI2

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AMC7834

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SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016

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Electrical Characteristics—General Specifications (continued)

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of

the product containing it. AVDD = DVDD = 5 V, AVCC = 5 V, AVSS = –5 V, IOVDD = 1.8 to 3.3 V, PAVDD = 5 V, AGND = DGND =

0 V, external 2.5 V reference, DAC output range = 0 to 5 V for all DACs, no load on the DACs, current sense inputs common

mode at 48 V, TA = –40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER REQUIREMENTS

IAVDD

AVDD supply current

POWER-MODE = 10.

AVDD = DVDD = 5.5 V, AVCC = 5.5 V

PAVDD = 20 V, AVSS = –5.5 V, IOVDD = 3.6 V

All monitoring channels enabled

Bipolar DACs in –5 to 0 V range

Auxiliary DACs in 0 to 5 V range

All DACs at 800h code. PA_ON in "ON" state

12.5

IAVCC

AVCC supply current

1.5

IAVSS

AVSS supply current

–3.5

–2.5

IDVDD

DVDD supply current

2.5

IIOVDD

IOVDD supply current

1.75

2.5

µA

IPAVDD

PAVDD supply current

170

250

µA

Power consumption

120.5

IAVDD

AVDD supply current

POWER-MODE = 00.

AVDD = DVDD = 5.5 V, AVCC = 5.5 V

PAVDD = 20 V, AVSS = –5.5 V, IOVDD = 3.6 V

All DACs in clamp mode at 0 V

PA_ON in "OFF" state

3.5

IAVCC

AVCC supply current

0.2

IAVSS

AVSS supply current

–2

IDVDD

DVDD supply current

2.5

IIOVDD

IOVDD supply current

1.75

µA

IPAVDD

PAVDD supply current

µA

Power consumption

(1)

Specified by design and characterization. Not tested during production.

(2)

SDO loaded with 10 pF load capacitance for SDO timing specifications.

6.8 Serial Interface Timing Requirements

(1) (2)

AVDD = DVDD = 5 V, AVCC = 5 V, AVSS = –5 V, PAVDD = 5 V, AGND = DGND = 0 V, external 2.5 V reference, DAC output

range = 0 to 5 V for all DACs, no load on the DACs, current sense inputs common mode at 48 V, TA = –40°C to +105°C

(unless otherwise noted)

IOVDD = 1.7 TO 2.7 V

IOVDD = 2.7 TO 3.6 V

UNIT

MIN

MAX

MIN

MAX

fSCLK

SCLK frequency

0.2

MHz

SCLK period

See Figure 1 and Figure 2.

100

66.67

tPH

SCLK pulse width high

tPL

SCLK pulse width low

tsu

SDI setup

SDI hold

t(ODZ)

SDO driven to tri-state

See Figure 2.

t(OZD)

SDO tri-state to driven

t(OD)

SDO output delay

tsu(CS)

CS setup

See Figure 1 and Figure 2

th(CS)

CS hold

t(IAG)

Inter-access gap

AMC7834 Datasheet(PDF) 13 Page - Texas Instruments

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