AMC7834 datasheet(6/97 Pages) TI2

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AMC7834

SLAS972B – NOVEMBER 2014 – REVISED MARCH 2016

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Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

IOVDD

—

IO supply voltage (1.7 V to 3.6 V). This pin sets the I/O operating voltage and threshold

levels.

PAVDD

—

Power supply for the PA_ON control signal (4 V to 20 V).

PA_ON

PA_ON is a synchronization signal capable of driving an external PMOS switch and

controlling the flow of drain current to a power amplifier (PA) transistor. The PA_ON pin has

an internal 120 k

Ω pull-up resistor to the PAVDD pin. The maximum output voltage is set by

the PAVDD pin and limited to 20 V. For drain voltages higher than 20 V, tying the PAVDD pin

to the AVDD pins and scaling the control signal externally is recommended. The PA_ON

signal state can be set through a register write but it can also be configured to trigger

automatically in the case of an ALARM event or when any of the SLEEP signals is

activated.

REF_CMP

I/O

Reference compensation capacitor connection. Connect a 4.7

μF capacitor between this

pin and the AGND4 pin for ADC reference compensation.

REF_IN

Reference input to the device. This pin can be connected to the REF_OUT pin to use the

device internal reference or alternatively to an external voltage reference source.

REF_OUT

Internal voltage reference output. Connect this pin directly to the REF_IN pin to operate the

device in internal reference mode. An external buffer amplifier with a high impedance input

is required to drive an external load. This pin can be left unconnected.

RESET

Active low reset input. Logic low on this pin causes the device to perform a hardware reset.

SCLK

Serial interface clock.

SDI

Serial interface data input. Data is clocked into the input shift register on each rising edge

of the SCLK pin.

SDO

Serial interface data output. The SDO pin is in high impedance when the CS pin is high.

Data is clocked out of the input shift register on each falling edge of the SCLK pin.

SENSE1+

Current sense 1 external sense resistor power connection

SENSE1–

Current sense 1 external sense resistor load connection

SENSE2+

Current sense 2 external sense resistor power connection

SENSE2–

Current sense 2 external sense resistor load connection

SENSE3+

Current sense 3 external sense resistor power connection

SENSE3–

Current sense 3 external sense resistor load connection

SENSE4+

Current sense 4 external sense resistor power connection

SENSE4–

Current sense 4 external sense resistor load connection

SLEEP1

Active high asynchronous power down digital input 1. The power down functions of this pin

are register configurable.

SLEEP2

Active high asynchronous power down digital input 2. The power down functions of this pin

are register configurable.

VCLAMP1

Power-on reset and clamp voltage control input for bipolar DACs 1 and 2. The resulting

power-on reset (POR) and clamp voltage value is given by Equation 1.

CLAMP = –3 × VCLAMP[1:2]

(1)

VCLAMP2

Power-on reset and clamp voltage control input for bipolar DACs 3 and 4. The resulting

POR and clamp voltage value is given by Equation 1.

Thermal Pad

—

The thermal pad is located on the bottom-side of the device package. The thermal pad

should be tied to the same potential as the AVSS pin for optimal thermal dissipation.

Alternatively, the thermal pad can be left unconnected.

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