PCM1861 datasheet(4/145 Pages) TI2

4 / 145 page

PCM1860, PCM1861, PCM1862

PCM1863, PCM1864, PCM1865

SLAS831D – MARCH 2014 – REVISED MARCH 2018

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Product Folder Links: PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865

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Revision History (continued)

•

Changed Mic Bias section; internal resistor is a terminating resistor................................................................................... 29

•

Deleted Figure 21 and Figure 22 from Mic Bias section ...................................................................................................... 29

•

Added note stating that clocks are required to be running in order to change PGA in the Programmable Gain

Amplifier section ................................................................................................................................................................... 31

•

Added text to clarify digital PGA update use in Programmable Gain Amplifier section ....................................................... 31

•

Changed note to clarify that the full scale moves to 4.2 VRMS when in differential mode at the end of the

Programmable Gain Amplifier section .................................................................................................................................. 31

•

Added new paragraph to end of Stereo PCM Sources section............................................................................................ 33

•

Changed Figure 33; clock tree updated and corrected ........................................................................................................ 36

•

Added new paragraph to target ADC, DSP1 and DSP2 clock rates in Device Clock Distribution and Generation section 36

•

Changed Clock Configuration and Selection section; relevant to hardware-controlled devices only .................................. 37

•

Added new paragraph regarding register MST_SCK_SRC to Clock Sources for Software-Controlled Devices section .... 37

•

Added note ("In Master Mode on..") to Clock Sources for Software-Controlled Devices section ........................................ 38

•

Changed Table 7; updated descriptions for clarity ............................................................................................................... 38

•

Changed "CLK_DIV_MST_SCK" to "CLK_DIV_SCK_BCK" and "CLK_DIV_MST_BCK" to "CLK_DIV_BCK_LRCK"

in Table 7 .............................................................................................................................................................................. 38

•

Changed Figure 34; clock tree updated and corrected ........................................................................................................ 38

•

Added "Target Clock Rates for ADC, DSP#1 and DSP#2" section ..................................................................................... 39

•

Changed Table 9; corrected PLL values by increasing P and R by 1, and corrected DSP1 clock divider values .............. 40

•

Changed Table 10; corrected PLL values by increasing P and R by 1, and corrected DSP1 clock divider values ............ 41

•

Changed Table 12; corrected PLL values by increasing P and R by 1, and corrected typo in DSP2 column title.............. 43

•

Changed Table 13; corrected PLL values by increasing P and R by 1, and corrected typo in DSP2 column title.............. 44

•

Added text "The clock tree must also be set..." to Software-Controlled Devices ADC Non-Audio MCK PLL Mode

section .................................................................................................................................................................................. 45

•

Changed PLL condition for D = 0000 to show 1 MHz

≤ (PLLCKIN / P) ≤ 20 MHz and 1 ≤ J ≤ 63 ...................................... 45

•

Changed PLL condition for D

≠ 0000 to show 6.667 MHz ≤ (PLLCLKIN / P) ≤ 20 MHz and 4 ≤ J ≤ 11 ............................. 45

•

Changed register numbers in Software-Controlled Devices Manual PLL Calculation section to align with the register

numbers in Table 14............................................................................................................................................................. 46

•

Changed Clock Halt and Error section; clock error moved to Clocks section, and interrupt capability deleted................... 46

•

Added Changing Clock Sources and Sample Rates section ............................................................................................... 47

•

Changed Secondary ADC: Energysense and Analog Control section; energysense signal detection not available in

active mode .......................................................................................................................................................................... 48

•

Changed text from "control signals up to 1.65 V" to "control signals up to 4.3 V" in the Secondary ADC Analog Input

Range section....................................................................................................................................................................... 49

•

Changed section title from "Secondary ADC DC Level Change Detection" to "Secondary ADC Controlsense DC

Level Change Detection" ...................................................................................................................................................... 49

•

Added text to the Secondary ADC Controlsense DC Level Change Detection section; controlsense is available in

both active and sleep modes................................................................................................................................................ 49

•

Added details to the Secondary ADC Controlsense DC Level Change Detection section regarding how to read

simple 8-bit values from the secondary ADC ....................................................................................................................... 49

•

Added new second paragraph to Energysense section ....................................................................................................... 50

•

Changed paragraph after Figure 38 in Energysense Signal Loss Flag section for clarity ................................................... 51

•

Changed Digital Decimation Filters section; clarified two different HPFs in the device ....................................................... 53

•

Changed text to clarify digital PGA update use in Digital PGA section................................................................................ 53

•

Changed Interrupt Controller section; deleted clock error as an interrupt source................................................................ 56

•

Changed text after Figure 44 in Interrupt Controller section; clarified INT pins all have same logic signal......................... 56

•

Added short description in the DIN Toggle Detection section.............................................................................................. 56

•

Added Clearing Interrupts section ........................................................................................................................................ 56

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