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PCM1861 Datasheet(PDF) 46 Page - Texas Instruments |
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PCM1861 Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 145 page  46 PCM1860, PCM1861, PCM1862 PCM1863, PCM1864, PCM1865 SLAS831D – MARCH 2014 – REVISED MARCH 2018 www.ti.com Product Folder Links: PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated The PLL can be programmed using page 0, registers 0x28 thru 0x2D. Turn on the PLL using page 0, register 0x28, D(0). The variable P can be programmed using page 0, register 0x29, D(3:0). The variable R can be programmed using page 0, register 0x2A, D(3:0). The variable J can be programmed using page 0, register 0x2B, D(5:0). The variable D is 14-bits and is programmed into two registers. The MSB portion is programmed using page 0, register 0x2D, D(5:0), and the LSB portion is programmed using page 0, register 0x2C, D(7:0). The variable D is set when the LSB portion is programmed. Values are programmed in the registers in Table 14. Table 14. PLL Coefficient Registers REGISTER FUNCTION BITS PLL_EN PLL enable, lock status and PLL reference Page 0, register 0x28 PLL_P PLL P Page 0, register 0x29 PLL_J PLL J Page 0, register 0x2B PLL_Dx PLL D Page 0, register 0x2C (least significant bits) Page 0, register 0x2D (most significant bits) PLL_R PLL R Page 0, register 0x2A 9.3.9.6 Clock Halt and Error The status of the halt and error detector can be read from register CLK_ERR_STAT (Page.0, 0x75). 9.3.9.7 Clock Halt and Error Detect The PCM186x has a clock error detection block inside that continues to monitor the ratio of BCK to LRCK. If a clock error is detected (such as an unexpected number of BCKs per LRCK), then the device goes into standby mode. If all the clocks are stopped going into the device, then the device shifts into sleep state, and begins Energysense signal detect mode. When a clock error occurs, the PCM186x starts the following sequence: 1. Mute audio output immediately (without volume ramp down) 2. Wait until proper clock is supplied (known as Clock Waiting State) 3. Restart clock detection. The PLL and all clock dividers are reconfigured with the result of the detection. 4. Start fade-in If the device stops transmitting data, the first step is to read CLK_ERR_STAT (Page.0 0x72). The least significant nibble shows the device status. Value 0x01 suggests Clock Waiting State, at which point the clock error status can be read in register STATE (Page.0 0x75). The clock detection logic is shown in Table 15. Table 15. Summary of Clock Detection Logic SCK BCK LRCK RESULT ACTION ACTIVE ACTIVE ACTIVE No error Normal operation ACTIVE ACTIVE HALT Clock error Enter clock waiting state ACTIVE HALT ACTIVE Clock error Enter clock waiting state ACTIVE HALT HALT Clock error Enter SLEEP HALT ACTIVE ACTIVE No error Enter BCK PLL mode HALT ACTIVE HALT Clock error Enter clock waiting state HALT HALT ACTIVE Clock error Enter clock waiting state HALT HALT HALT Clock error Enter SLEEP |
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